Impacts of gate-oxide breakdown on power-gated SRAM

Abstract

This paper presents a detailed analysis on the impacts of various gate-oxide breakdown (BD) paths in column-based header- and footer-gated SRAMs. It is shown that with gate-oxide BD, the read static noise margin (RSNM) and write margin (WM) degrade in general. Pass-transistor gate-oxide BD between WL and BL is shown to degrade read/write margin and performance, and to affect other healthy cells along the same column as well. The effects of gate-to-source BD of cell transistors are shown to confine to the individual cells, while multiple cells suffering cell transistor drain-to-drain BD in a column could cumulatively affect VVDD (header structure) or VVSS (footer structure), thus influencing other cells in the same column. In particular, we show that the gate-oxide BD of the power-switches has severe and even detrimental effects on the margin, stability, and performance of the SRAM array. Several techniques to mitigate the power-switch gate-oxide BD have been evaluated, including adding a gate series resistance to the power-switch, dual threshold voltage power-switch, thick gate-oxide power-switch, and dual gate-oxide thickness (dual-T(OX)) power-switch. It is shown that the dual-Tox power-switch improves the time-to-dielectric-breakdown (7(BD)) of the power-switch while maintaining the performance without side effect. (C) 2010 Elsevier Ltd. All rights reserved.