標題: | Impacts of gate-oxide breakdown on power-gated SRAM |
作者: | Yang, Hao-I Hwang, Wei Chuang, Ching-Te 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
關鍵字: | Gate-oxide breakdown;Power-gating technology;SRAM |
公開日期: | 1-一月-2011 |
摘要: | This paper presents a detailed analysis on the impacts of various gate-oxide breakdown (BD) paths in column-based header- and footer-gated SRAMs. It is shown that with gate-oxide BD, the read static noise margin (RSNM) and write margin (WM) degrade in general. Pass-transistor gate-oxide BD between WL and BL is shown to degrade read/write margin and performance, and to affect other healthy cells along the same column as well. The effects of gate-to-source BD of cell transistors are shown to confine to the individual cells, while multiple cells suffering cell transistor drain-to-drain BD in a column could cumulatively affect VVDD (header structure) or VVSS (footer structure), thus influencing other cells in the same column. In particular, we show that the gate-oxide BD of the power-switches has severe and even detrimental effects on the margin, stability, and performance of the SRAM array. Several techniques to mitigate the power-switch gate-oxide BD have been evaluated, including adding a gate series resistance to the power-switch, dual threshold voltage power-switch, thick gate-oxide power-switch, and dual gate-oxide thickness (dual-T(OX)) power-switch. It is shown that the dual-Tox power-switch improves the time-to-dielectric-breakdown (7(BD)) of the power-switch while maintaining the performance without side effect. (C) 2010 Elsevier Ltd. All rights reserved. |
URI: | http://dx.doi.org/10.1016/j.mejo.2010.08.020 http://hdl.handle.net/11536/25947 |
ISSN: | 0026-2692 |
DOI: | 10.1016/j.mejo.2010.08.020 |
期刊: | MICROELECTRONICS JOURNAL |
Volume: | 42 |
Issue: | 1 |
起始頁: | 101 |
結束頁: | 112 |
顯示於類別: | 期刊論文 |