高可靠度奈米級靜態隨機存取記憶體設計： 可靠度分析與改善技術

Abstract

本論文針對高可靠度奈米級隨機存取記憶體提出分析與討論，並提出可改善奈米級隨機存取記憶體可靠度的技術。我們特別著重分析偏壓溫度效應與閘極崩毀兩種現象對採用功率閘的奈米級隨機存取記憶體所可能產生的影響，我們分析的範圍包括記憶體單元的穩定度與被寫入能力、記憶體的讀寫路徑、時序控制電路、和功率閘等。研究分析結果顯示，若功率閘受到偏壓溫度效應或閘極崩毀影響，則將會嚴重的影響記憶體的穩定度；若時序控制電路受到偏壓溫度效應響，則將導致記憶體的讀寫效率下降。基於以上分析研究結果，我們更提出改善記憶體可靠的方法與技術：我們提出利用兩種不同厚度的功率閘來延長功率閘的閘極壽命，一方面使閘極崩毀較不容易發生，另一方面也可以維持功率閘的效率與一般單種厚度功率閘相同；我們也提出降低偏壓溫度效應對奈米級隨機存取記憶體的方法，例如使用兩種不同臨界電壓的記憶體單元、採用可維持資料的功率閘技術來減少記憶體陣列的跨壓。我們也更進一步地提出可在低電壓可操作的記憶體單元，此記憶體單元共由八個電晶體所組成，藉由交叉式選取與適應性的需接地端電位控制，此記憶體單元不會被讀寫運作時產生的雜訊所干擾；藉由蒙地卡羅發法的分析，我們所提出的記憶體較一般傳統的記憶體在雜訊邊界上有約1.2倍的改善。我們也利用聯電55nm標準CMOS製程完成一個512Kb的驗證晶片，這個驗證晶片的大小為1100.3×1434.50 um2。量測結果顯示，我們所提出的設計可以正常的操作於1.5V至0.6V之間，在不同的操作電壓下，此驗證晶片的最高可操作頻率範圍分別為：在1.5V 下的1.143GHz至1.2V的943MHz與0.6V 下的209MHz。

This thesis discusses the reliability and tolerance techniques for the robust nanoscale SRAM design. It provides comprehensive analyses on the impacts of Bias Temperature Instability (BTI) and gate-oxide breakdown on power-gated SRAMs, including the stability and Write-ability of cells, Read/Write access paths, replica timing control circuits, and the data-retention power-gating devices. We show that the degradation of power-gating switches induced by BTI or gate-oxide breakdown significantly affects the stability of SRAM arrays. The degradation of timing control circuits caused by BTI results in SRAM performance decreasing. Moreover, based on these analyses, the degradation tolerance techniques are also presented. We provide the dual gate-oxide thickness power-switch to improve the time-to-dielectric-breakdown (TBD) of the power-switch while maintaining the performance without side effect. We also present some techniques to mitigate SRAM degradation induced by BTI, including dual-VTH cells, and the banking data-retention power-gating technique to reduce the stress voltage during Standby mode. Furthermore, a low VMIN disturb-free 8T SRAM cell with cross-point Write structure and adaptive VVSS control is introduced. The Monte Carlo simulation results show that the proposed 8T cell improve Static Noise Margin about 120% comparing with the conventional 6T cell. A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology, and the chip area is 1100.3×1434.50 um2. The measurement results demonstrate operating frequency of 1.143GHz at 1.5V, 943MHz at 1.2V, and 209MHz at 0.6V.