Speed up of rendering pipeline by deferred lighting and triple queue structure
| dc.citation.epage | 1333 | en_US |
| dc.citation.issue | 22 | en_US |
| dc.citation.spage | 1332 | en_US |
| dc.citation.volume | 37 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | Liang, BS | en_US |
| dc.contributor.author | Jen, CW | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:43:20Z | |
| dc.date.available | 2014-12-08T15:43:20Z | |
| dc.date.issued | 2001-10-25 | en_US |
| dc.description.abstract | Redundant operations and stalls prevent a rendering pipeline from full-speed operation. To speed up the rendering pipeline, a triple queue structure is proposed to smooth the pipeline and to obtain benefit from deferred lighting. The results of cycle-accurate simulation show that the proposed structure can reduce rendering cycles to 52.9% in small size queues. | en_US |
| dc.identifier.doi | 10.1049/el:20010901 | en_US |
| dc.identifier.issn | 0013-5194 | en_US |
| dc.identifier.journal | ELECTRONICS LETTERS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1049/el:20010901 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/29335 | |
| dc.identifier.wosnumber | WOS:000171943100011 | |
| dc.language.iso | en_US | en_US |
| dc.title | Speed up of rendering pipeline by deferred lighting and triple queue structure | en_US |
| dc.type | Article | en_US |