THE EFFECT OF LAYOUT, SUBSTRATE WELL BIASES, AND TRIGGERING SOURCE LOCATION ON LATCHUP TRIGGERING CURRENTS IN BULK CMOS CIRCUITS
| dc.citation.epage | 279 | en_US |
| dc.citation.issue | 4 | en_US |
| dc.citation.spage | 269 | en_US |
| dc.citation.volume | 32 | en_US |
| dc.citation.woscount | 0 | |
| dc.contributor.author | YANG, YH | en_US |
| dc.contributor.author | WU, CY | en_US |
| dc.contributor.department | 交大名義發表 | zh_TW |
| dc.contributor.department | 電控工程研究所 | zh_TW |
| dc.contributor.department | National Chiao Tung University | en_US |
| dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:05:51Z | |
| dc.date.available | 2014-12-08T15:05:51Z | |
| dc.date.issued | 1989-04-01 | en_US |
| dc.identifier.issn | 0038-1101 | en_US |
| dc.identifier.journal | SOLID-STATE ELECTRONICS | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/4389 | |
| dc.identifier.wosnumber | WOS:A1989U203600002 | |
| dc.language.iso | en_US | en_US |
| dc.title | THE EFFECT OF LAYOUT, SUBSTRATE WELL BIASES, AND TRIGGERING SOURCE LOCATION ON LATCHUP TRIGGERING CURRENTS IN BULK CMOS CIRCUITS | en_US |
| dc.type | Article | en_US |
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