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THIN OXIDE GROWN ON HEAVILY CHANNEL-IMPLANTED SUBSTRATE BY USING A LOW-TEMPERATURE WAFER LOADING AND N2 PRE-ANNEALING PROCESS

dc.citation.epage1730en_US
dc.citation.issue12en_US
dc.citation.spage1725en_US
dc.citation.volume36en_US
dc.citation.woscount0
dc.contributor.authorWU, SLen_US
dc.contributor.authorLEE, CLen_US
dc.contributor.authorLEI, TFen_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.date.accessioned2014-12-08T15:04:16Z
dc.date.available2014-12-08T15:04:16Z
dc.date.issued1993-12-01en_US
dc.description.abstractIn this paper, we present high integrity thin oxides grown on the channel implanted substrate (greater-than-or-equal-to 3 x 10(17) cm-3) and heavily doped substrate (greater-than-or-equal-to 1 x 10(20) cm-3) by using a low-temperature wafer loading and N2 pre-annealing process. The presented thin oxide grown on the channel implanted substrate exhibits a very low interface state density (less-than-or-equal-to 1 x 10(10) cm-2 eV-1) and a very high intrinsic dielectric breakdown field (greater-than-or-equal-to 15 MV/cm). It also shows a lower charge trapping rate and interface state generation rate than the conventional thermal oxide. For the thin oxide grown on the heavily-doped substrate by using the proposed recipe, the implantation-induced damage close to the silicon surface can be almost annealed out. The presented heavily-doped oxide shows much better dielectric characteristics, such as the dielectric breakdown field and the charge-to-breakdown, as compared to the conventional heavily-doped oxide.en_US
dc.identifier.issn0038-1101en_US
dc.identifier.journalSOLID-STATE ELECTRONICSen_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/2776
dc.identifier.wosnumberWOS:A1993ML44200010
dc.language.isoen_USen_US
dc.titleTHIN OXIDE GROWN ON HEAVILY CHANNEL-IMPLANTED SUBSTRATE BY USING A LOW-TEMPERATURE WAFER LOADING AND N2 PRE-ANNEALING PROCESSen_US
dc.typeArticleen_US

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