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The effect of IrO2-IrO2-Hf-LaAlO3 gate dielectric on the bias-temperature instability of 3-d GOI CMOSFETs

dc.citation.epage409en_US
dc.citation.issue6en_US
dc.citation.spage407en_US
dc.citation.volume26en_US
dc.citation.woscount3
dc.contributor.authorYu, DSen_US
dc.contributor.authorLiao, CCen_US
dc.contributor.authorCheng, CFen_US
dc.contributor.authorChin, Aen_US
dc.contributor.authorLi, MFen_US
dc.contributor.authorMcAlister, SPen_US
dc.contributor.department奈米科技中心zh_TW
dc.contributor.departmentCenter for Nanoscience and Technologyen_US
dc.date.accessioned2014-12-08T15:18:59Z
dc.date.available2014-12-08T15:18:59Z
dc.date.issued2005-06-01en_US
dc.description.abstractWe have studied the bias-temperature instability of three-dimensional self-aligned metal-gate/high-&kappa;/Germanium-on-insulator (GOI) CMOSFETs, which were integrated on underlying 0.18 &mu; m CMOSFETs. The devices used IrO2-IrO2-Hf dual gates and a high-&kappa; LaAlO3 gate dielectric, and gave an equivalent-oxide thickness (EOT) of 1.4 nm. The metal-gate/high-&kappa;/GOI p-and n-MOSFETs displayed threshold voltage (V-t) shifts of 30 and 21 mV after 10 MV/cm, 85 &DEG; C stress for 1 h, comparable with values for the control two-dimensional (2-D) metal-gate/high-&kappa;-Si CMOSFETs. An extrapolated maximum voltage of -1.2 and 1.4 V for a ten-year lifetime was obtained from the bias-temperature stress measurements on the GOI CMOSFETs.en_US
dc.identifier.doi10.1109/LED.2005.848130en_US
dc.identifier.issn0741-3106en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2005.848130en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/13641
dc.identifier.wosnumberWOS:000229522000021
dc.language.isoen_USen_US
dc.subjectbias-temperature instability (BTI)en_US
dc.subjectgermaniumon-insulator (GOI)en_US
dc.subjecthigh kappaen_US
dc.subjectLaAlO3en_US
dc.subjectmetal gateen_US
dc.subjectthree-dimensional (3-D)en_US
dc.titleThe effect of IrO2-IrO2-Hf-LaAlO3 gate dielectric on the bias-temperature instability of 3-d GOI CMOSFETsen_US
dc.typeArticleen_US

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