Browsing by Author "Chen, WJ"

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3D GOI CMOSFETs with novel IrO2(Hf) dual gates and high-kappa dielectric on 1P6M-0.18 mu m-CMOS
(2004)
Yu, DS
;
Chin, A
;
Laio, CC
;
Lee, CF
;
Cheng, CF
For the first time, we demonstrate 3D integration of self-aligned IrO2(Hf)/LaAlO3/GOI CMOSFETs above 0.18 pm Si CMOSFETs. At EOT=1.4nm, the novel IrO2(Hf) dual gates (4.4 and 5.1 eV workfunction) on control 2D LaAlO3/Si devices have high electron and hole mobilities of 203 and 67 cm(2)/Vs. On the 3D structure the LaAlO3/GOI shows even higher 389 and 234 cm(2)/Vs mobilities, and process compatibility with current Si VLSI. The higher drive current, larger integration density, shorter interconnects distance, and simple process of 3D approach can help solve the AC power issue and 2D scaling limitation.
A multiobjective model for non-point source pollution control for an off-stream reservoir catchment
(2003)
Kao, JJ
;
Chen, WJ
;
環境工程研究所
;
Institute of Environmental Engineering
Phosphorus loads from agricultural non-point source pollution (NPSP) significantly degrade reservoir water quality, making adequate control of agricultural NPSP necessary for improving the water quality. Controlling NPSP is generally accomplished using various Best Management Practices (BMPs). The present study applies the Agricultural Non-Point Source Pollution (AGNPS) model to simulate NPSP loading and BMP efficiencies and establishes an enhanced multiobjective mixed-integer programming model for NPSP control strategy analyses based on these results. Cost, phosphorus load, sediment load and equity are the four major objectives considered. A case study for the Posan reservoir is presented. Four commonly proposed and applicable BMPs are chosen. Non-inferior solutions obtained using the constraint method and trade-off relationships among different control objectives are described and discussed. Compared with a previously proposed fertilizer control model, results show that the model established herein is more cost-effective and achieves better phosphorus and sediment loading reduction and equity goals. Furthermore, the current model is expected to facilitate decision-making analysis for development of an appropriate cost-sharing program to encourage adoption of appropriate BMPs by farmers.
Characterization of Si/SiGe heterostructures on Si formed by solid phase reaction
(2002-03-01)
Huang, CH
;
Chin, A
;
Chen, WJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have characterized the Si/Si(0.6)Ge(0.4) heterostructure formed by two-step solid-phase reaction. Single crystalline behavior is evidenced by X-ray diffraction. In sharp contrast to conventional strain-relaxed SiGe, an extremely smooth surface close to the Si substrate is measured by cross-sectional transmission electron microscopy and atomic force microscopy. Good material quality is further evidenced from the near identical current-voltage characteristics for thermal oxide grown on Si/Si(0.6)Ge(0.4) and on the Si control sample. (C) 2002 The Electrochemical Society.
Device level characterization for energy bandgap of strain-relaxed SiGe and oxide/SiGe barrier height
(2004)
Huang, CH
;
Yu, DS
;
Chin, A
;
Chen, WJ
;
McAlister, SP
From the interface state density with energy plot measured by capacitance-voltage characteristics, we have derived the energy bandgap of strain-relaxed Si1-xGex (x: 0.4 and 0.7) for the first time at the device level, because the allowed states increases sharply near the conduction and valence bandedges. We find that the energy bandgap of SiGe is reduced from 0.90 to 0.83 eV as the Ge composition increases from Si0.6Ge0.4 to Si0.3Ge0.7. In contrast, similar oxide/Si1-xGex conduction-band barrier heights of similar to3.1 eV have been obtained for both SiGe cases using Fowler-Nordheim tunneling. These results are in good agreement with published theoretical and experimental data from material level characterization. The device level characterization is especially important because the SiGe composition and material property may be altered after thermal cycles for device fabrication. (C) 2004 The Electrochemical Society.
Electrical characteristics of high quality La2O3 gate dielectric with equivalent oxide thickness of 5 angstrom
(2000-07-01)
Wu, YH
;
Yang, MY
;
Chin, A
;
Chen, WJ
;
Kwei, CM
Electrical and reliability properties of ultrathin La2O3 gate dielectric have been investigated. The measured capacitance of 33 Angstrom La2O3 gate dielectric is 7.2 mu F/cm(2) that gives an effective K value of 27 and an equivalent oxide thickness of 4.8 Angstrom. Good dielectric integrity is evidence from the low leakage current density of 0.06 A/cm(2) at -1 V, high effective breakdown field of 13.5 MV/cm, low interface-trap density of 3 x 10(10) eV-1/cm(2), and excellent reliability with more than 10 years lifetime even at 2 V bias. In addition to high K, these dielectric properties are very close to conventional thermal SiO2.
Face recognition and tracking for human-robot interaction
(2004)
Song, KT
;
Chen, WJ
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper presents a design and experimental study of human-robot interaction via face recognition and image tracking. A new architecture is proposed for fast face recognition of family members. In the proposed system, each family member has his/her own RBF neural networks. Each neural network is only responsible for recognizing its trained member. Consequently, the database is small and the processing time required for face recognition is minimized. A recognition rate of 94% has been achieved, an improvement relative to conventional approaches. In order to detect and track a person, we also developed an algorithm for detecting multiple faces in a scene based on division of skin and hair color regions. The face recognition and image tracking system has been integrated to an experimental mobile robot. Practical experiments reveal that the robot demonstrates real-time face recognition and tracking performance.
Formation of Ni germano-silicide on single crystalline Si0.3Ge0.7/Si
(2002-08-01)
Lin, CY
;
Chen, WJ
;
Lai, CH
;
Chin, A
;
Liu, J
We have studied the Ni and Co germano-silicide on Si0.3Ge0.7/Si. The Ni germano-silicide shows a low sheet resistance of 4-6 Omega/square on both P+N and N+P junctions, which is much smaller than Co germano-silicide. In addition, small junction leakage currents of 3 x 10(-8) A/cm(2) and 2 x 10(-7) A/cm(2) are obtained for Ni germano-silicide on P+ N and N+ P junctions, respectively. The good germano-silicide integrity is due to the relatively uniform thickness as observed by cross-sectional TEM.
Fully silicided NiSi and germanided NiGe dual gates on SiO2 n- and p-MOSFETs
(2003-12-01)
Yu, DS
;
Wu, CH
;
Huang, CH
;
Chin, A
;
Chen, WJ
We have fabricated the fully silicided NiSi and germanided NiGe dual gates n- and p-MOSFETs on 1.9 nm thick SiO2 gate dielectric. The extracted work functions of fully NiSi and NiGe gates from thickness-dependent flat band voltage were 4.55 and 5.2 eV respectively, which may provide possible wide work function tuning using NiSi1-xGex. In additional to the lower gate current than Al gate n- and p-MOSFETs, the fully silicided NiSi and germanided NiGe gates MOSFETs show electron and hole mobilities close to universal mobility values with special advantage of process compatible to current VLSI fabrication line.
Fully silicided NiSi and germanided NiGe dual gates on SiO2/Si and Al2O3/Ge-on-insulator MOSFETs
(2003)
Huang, CH
;
Yu, DS
;
Chin, A
;
Wu, CH
;
Chen, WJ
We demonstrate for the first time fully silicided NiSi (4.55eV) and germanided NiGe (5.2eV) dual gates on 1.9nm-SiO2/Si and Al2O3/Ge-On-Insulator (GOI) MOSFETs (EOT = 1.7nm). In additional to the comparable gate current and time-to-breakdown with AI gate C-MOSFETs, the fully NiSi and NiGe gates on SiO2/Si show mobility close to universal mobility while on Al2O3/GOI show similar to2.0X higher peak electron and hole mobility than Al on Al2O3/Si with special advantage of NiSi and NiGe compatible to current VLSI process line.
High hole mobility of Al2O3 mosfets on dislocation free Ge-on-insulator wafers
(2004)
Chin, A
;
Yu, DS
;
Wu, CH
;
Huang, CH
;
Chen, WJ
The much degraded mobility, high-kappa dielectric crystallization, and EOT reduction after processing are the primary limitations of high-kappa gate dielectric MOSFETs. We have fabricated the high-kappa Al2O3 MOSFET on Geon-Insulator to enhance the hole mobility. The measured hole mobility with 1.7 nm EOT is 73 cm(2)/Vs at E-eff of 1 MV/cm, which is 2.5 times and 1.3 times higher than and Al2O3/Si control devices and SiO2/Si universal mobility, respectively. In additional to good dielectric reliability, the low temperature process (less than or equal to500degreesC) can also avoid high-kappa dielectric crystallization and EOT reduction by O-2 or moisture penetration through high-kappa dielectric.
High quality epitaxial Si grown by a simple low pressure chemical vapor deposition at 550 degrees C
(1996-09-09)
Chin, A
;
Lin, BC
;
Chen, WJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have designed a simple-hot wall low pressure chemical vapor deposition (LPCVD) system to grow high quality epitaxial Si films from 550 to 900 degrees C. The epitaxial film has been examined by scan electron microscopy for surface morphology, and by x-ray diffraction and cross-sectional transmission electron microscopy for crystallinity. Its quality has been found comparable to that of the substrate. Reduction of moisture and oxygen in the ambient is critical to the success of the growth at low temperatures. A combination of a leak-tight LPCVD reactor, a high flow rate Of 61/min of H-2 purge, and a pre-bake at high temperature of 950 degrees C has been used to achieve the reduction of moisture and oxygen. Degraded films form with increasing full width at half maximum of x-ray diffraction peak when a pre-bake at lower temperature is used. (C) 1996 American Institute of Physics.
High quality epitaxial Si grown by a simple low pressure chemical vapor deposition at 550 degrees C
(1996-09-09)
Chin, A
;
Lin, BC
;
Chen, WJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We have designed a simple-hot wall low pressure chemical vapor deposition (LPCVD) system to grow high quality epitaxial Si films from 550 to 900 degrees C. The epitaxial film has been examined by scan electron microscopy for surface morphology, and by x-ray diffraction and cross-sectional transmission electron microscopy for crystallinity. Its quality has been found comparable to that of the substrate. Reduction of moisture and oxygen in the ambient is critical to the success of the growth at low temperatures. A combination of a leak-tight LPCVD reactor, a high flow rate Of 61/min of H-2 purge, and a pre-bake at high temperature of 950 degrees C has been used to achieve the reduction of moisture and oxygen. Degraded films form with increasing full width at half maximum of x-ray diffraction peak when a pre-bake at lower temperature is used. (C) 1996 American Institute of Physics.
High quality La2O3 and Al2O3 gate dielectrics with equivalent oxide thickness 5-10 angstrom
(2000)
Chin, A
;
Wu, YH
;
Chen, SB
;
Liao, CC
;
Chen, WJ
High quality La2O3 and Al2O3 are fabricated with EOT of 4.8 and 9.6 Angstrom, leakage current of 0.06 and 0.4A/cm(2) and D-it of both 3x10(10) eV(-1)/cm(2), respectively. The high K is further evidenced from high MOSFET's I-d and g(m) with low I-off Good SILC and Q(BD) are obtained and comparable with. SiO2. The low EOT is due to the high thermodynamic stability in contact with Si and stable after H-2 annealing up to 550 degrees C.
High-kappa Ir/TiTaO/TaN capacitors suitable for analog IC applications
(2005-07-01)
Chiang, KC
;
Huang, CC
;
Chin, A
;
Chen, WJ
;
McAlister, SP
We have developed novel high-k Ir/TiTaO/TaN capacitors which have high-capacitance density (10.3 fF/mu m(2)), small leakage current at 2 V (1.2 x 10(-8) A/cm(2)), and low voltage linearity of the capacitance (89 ppm/V-2). These excellent results meet the TTRS roadmap requirements for precision -analog capacitors for the year 2018. The good performance is due to the very high K (45) achieved in the TiTaO dielectric and the high work-function (5.2 eV) provided by the Ir electrode.
High-quality thermal oxide grown on high-temperature-formed SiGe
(2000-05-01)
Wu, YH
;
Chen, SB
;
Chin, A
;
Chen, WJ
;
電子工程學系及電子研究所
We have developed a high-quality gate oxide on Si0.6Ge0.4 with a 30 Angstrom Si top layer. The good oxide integrity comparable to conventional thermal oxide is demonstrated by the low interface trap density of 6.2 X 10(10) eV(-1) cm(-2), low bride charge of 5.8 X 10(10) cm(-2), small leakage current at 3.3 V of 4.2 x 10(-8) A/cm(2), high breakdown field of 13.8 MV/cm, good charge-to-breakdown of 5.2 C/cm(2), and small stress-induced leakage current. This good oxide integrity is directly related to our previously developed SiGe formed by solid phase epitaxy at high temperatures that is stable during thermal oxidation. This simple process is fully compatible with existing very large scale integration technology. (C) 2000 The Electrochemical Society. S0013-4651(99)10-038-7. All rights reserved.
Improved electrical characteristics of CoSi2 using HF-vapor pretreatment
(1999-05-01)
Wu, YH
;
Chen, WJ
;
Chang, SL
;
Chin, A
;
Gwo, S
We have developed a simple process to form epitaxial CoSi2 for shallow junction. Prior to metal deposition, the patterned wafers were treated with HF-vapor passivation. As observed by scanning tunneling microscopy (STM), this HF, treatment drastically improves the native oxide-induced sur face roughness. The epitaxial behavior was confirmed by cross-sectional transmission electron microscopy (TEM), Decreased sheet resistance and leakage current, and improved thermal stability are displayed by the HF treated samples, which is consistent with STM and TEM results.
Improved electrical characteristics of CoSi2 using HF-vapor pretreatment
(1999-05-01)
Wu, YH
;
Chen, WJ
;
Chang, SL
;
Chin, A
;
Gwo, S
We have developed a simple process to form epitaxial CoSi2 for shallow junction. Prior to metal deposition, the patterned wafers were treated with HF-vapor passivation. As observed by scanning tunneling microscopy (STM), this HF, treatment drastically improves the native oxide-induced sur face roughness. The epitaxial behavior was confirmed by cross-sectional transmission electron microscopy (TEM), Decreased sheet resistance and leakage current, and improved thermal stability are displayed by the HF treated samples, which is consistent with STM and TEM results.
Improved electrical characteristics of CoSi2 using HF-vapor pretreatment
(1999-07-01)
Wu, YH
;
Chen, WJ
;
Chang, SL
;
Chin, A
;
Gwo, S
We have developed a simple process to form epitaxial CoSi2 for shallow junction. Prior to metal deposition, the patterned wafers were treated with HF-vapor passivation. As observed hy scanning tunneling microscopy (STM), this HF treatment drastically improves the native oxide-induced surface roughness. The epitaxial behavior was confirmed by cross-sectional transmission electron microscopy (TEM). Decreased sheet resistance and leakage current, and improved thermal stability are displayed by the HF treated samples, which is consistent with STM and TEM results.
Improvement of resolution by maximum entropy linear image restoration for NiSi2/Si interface
(1999)
Chen, FR
;
Kai, JJ
;
Chang, L
;
Wang, JY
;
Chen, WJ
A linear imaging constrained-maximum entropy method has been developed to extend the resolution from a series of defocused high-resolution images and one diffraction pattern. Our method is basically the Gerchberg-Saxton algorithm, which restores spatial information by imposing real space and Fourier space constraints cyclically. A constrained-maximum entropy method (constrained-MEM) was developed for real space constraints. This constrained-MEM finds an optimum solution of phases such that simulated images resemble the experimental image under some constraints in real space. These constraints include conservation of charge as well as a minimum of the chi(2) function, which is a measure of the level of satisfaction between simulated images and experimental images. For the Fourier space constraint, the square root intensities of diffraction spots were substituted. In this paper, we demonstrate that this method is able to extend the resolution from a series of high-resolution images and one diffraction pattern from a periodic NiSi2/Si interface. The atomic structure of the NiSi2/Si interface can be directly read out from the MEM image without a priori knowledge of the interface.
La2O3/Si0.3Ge0.7 p-MOSFETs and Ni germano-silicide
(2003)
Huang, CH
;
Lin, CY
;
Li, HY
;
Chen, WJ
;
Chin, A
We have used Si0.3Ge0.7 to improve the hole mobility of La2O3 p-MOSFETs. A hole mobility of 55 cm(2)/V's in nitrided La2O3/Si0.3Ge0.7 p-MOSFET is measured and 1.8 times higher than the 31 cm(2)/V-s mobility in nitrided La2O3/Si control p-MOSFET. The Ni germano-silicide shows a low sheet resistance of 4-6 Omega/rectangle and small junction leakage currents of 3x10(-8) A/cm(2) and 2x10(-7) A/cm(2) for respective P+N and N+P junctions.