Browsing by Author "Luo, Guang-Li"

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A Comprehensive Study of Ge1-xSix on Ge for the Ge nMOSFETs with Tensile Stress, Shallow Junctions and Reduced Leakage
(2009)
Luo, Guang-Li
;
Huang, Shih-Chiang
;
Chung, Cheng-Ting
;
Heh, Dawei
;
Chien, Chao-Hsin
For the first time, growth of high-quality Ge-rich Ge1-xSix (0 <= x <= 0.14) layers on Ge substrate was demonstrated. An effective suppression of the phosphorus diffusion in Ge1-xSix and a better thermal stability of the nickel germanide on Ge1-xSix were observed. A higher rectifying ratio with a reduced diode leakage current in n(+)-Ge1-xSix/p-Ge1-xSix is compared with n(+)-Ge/p-Ge. These results indicate that it is suitable for Ge1-xSix to be used as source/drain (S/D) to fabricate the uniaxial tensile-strained channel Ge nMOSFETs.
An AlGaAs/InGaAs HEMT Grown on Si Substrate with Ge/GexSi1-x Metamorphic Buffer Layers
(2008)
Chang, Edward Yi
;
Lin, Yueh-Chin
;
Hsiao, Yu-Lin
;
Hsieh, Y. C.
;
Chang, Chia-Yuan
An AlGaAs/InGaAs HEMT grown on Si substrate with Ge/GexSi1-x buffer is demonstrated. The Ge/GexSi1-x metamorphic buffer layer used in this structure was only 1.0 mu m thick. The electron mobility in the In0.18Ga0.82As channel of the HEMT sample was 3,550 cm(2)/Vs. After fabrication, the HEMT device demonstrated a saturation current of 150 mA/mm and a maximum transconductance of 155 mS/mm. The well behaved characteristics of the HEMT device on the Si substrate are believed to be due to the very thin buffer layer achieved and the lack of the antiphase boundaries (APBs) formation and Ge diffusion into the GaAs layers. Index Terms: HEW GaAs on Si, SiGe buffer layer
An oxide-buffered BE-MANOS charge-trapping device and the role of Al2O3
(2008)
Lai, Sheng-Chih
;
Lue, Hang-Ting
;
Liao, Chien-Wei
;
Huang, Yu-Fong
;
Yang, Ming-Jui
The role of Al2O3 in MANOS device is critically examined, and we conclude that its primary function is to reduce gate injection during erase operation. By itself, Al2O3 cannot stop charge leakage from the charge-trapping nitride layer. Furthermore, Al2O3 provides no magic during the erase operation, and MANOS erases very slowly through charge de-trapping. BE-SONOS [1], with the band engineered ONO tunneling layers, provides efficient channel hole injection for erase. BE-MANOS [2] should be an ideal combination with fast erase and good reliability. However, it shows poor data retention. By inserting a SiO2 buffer layer between Al2O3 and the SiN storage layer, the oxide-buffered BE-MANOS shows good performance and good reliability. The EOT scalability is also investigated.
Body-Tied Germanium FinFETs Directly on a Silicon Substrate
(2012-12-01)
Chen, Che-Wei
;
Chung, Cheng-Ting
;
Luo, Guang-Li
;
Chien, Chao-Hsin
;
電子工程學系及電子研究所
We fabricated body-tied Ge p-channel fin field-effect transistors (p-FinFETs) directly on a Si substrate with a high-kappa/metal gate stack. This scheme is fully compatible with Si standard processing. The FinFET structure has excellent control on the channel potential and thus can improve the short-channel effect. The diode with p(+)-Ge/n-Si heterojunctions illustrates a remarkably high I-ON/I-OFF > 10(6) despite the presence of misfit dislocations at the interface. The high-hole-mobility body-tied Ge p-FinFETs with a fin width W-Fin of similar to 40 nm and a mask channel length L-Mask of 120 nm depict a driving current of 22 mu A/mu m at V-G = -2 V and a low OFF-current of 3 nA/mu m at V-G = 2 V. The subthreshold characteristics with a swing of 228 mV/dec and drain-induced barrier lowering of 288 mV/V are demonstrated.
Body-Tied Germanium Tri-Gate Junctionless PMOSFET With In-Situ Boron Doped Channel
(2014-01-01)
Chen, Che-Wei
;
Chung, Cheng-Ting
;
Tzeng, Ju-Yuan
;
Chang, Pang-Sheng
;
Luo, Guang-Li
In this letter, we demonstrate body-tied Ge tri-gate junctionless (JL) p-channel MOSFETs directly on Si. Our tri-gate JL-PFET exhibits higher current than the conventional inversion-mode transistor through in-situ heavily doped technique and trimming down Ge fin width. We show that the JL-PFET with tri-gate structure has excellent I-ON/I-OFF ratio and good short channel effect control on the channel potential. The current ratio is of similar to 6 x 10(3) (I-D) at V-DS = -0.1 V, V-GS = -3, and 0 V. The relatively low OFF-current is of 6 nA/ mu m at V-DS = -0.1 V and V-GS = 0 V. The subthreshold swing of 203 mV/decade and drain induced barrier lowering of 220 mV/V are reported at L-G = 120 nm.
C-V characteristics of epitaxial germanium metal-oxide-semiconductor capacitor on GaAs substrate with ALD Al2O3 dielectric
(2012-09-01)
Tang, Shih Hsuan
;
Kuo, Chien I.
;
Hai Dang Trinh
;
Hudait, Mantu
;
Chang, Edward Yi
Epitaxial germanium metal-oxide-semiconductor capacitors (MOSCAP) were fabricated on GaAs substrate using atomic layer deposited Al2O3 gate dielectric with surface treatments including pure HF and HF plus rapid thermal oxidation (RTO). The electrical characteristics of 10 nm Al2O3/Ge MOSCAP showed p-type behavior with excellent C-V responses and low leakage current. Interface state density in the order of 10(11) eV(-1) cm(-2) was determined from the conductance method and the HF plus RTO treatment exhibits better Al2O3/Ge interface quality than that of pure HF treatment. (C) 2012 Elsevier B.V. All rights reserved.
Characteristics of atomic-layer-deposited Al(2)O(3) high-k dielectric films grown on Ge substrates
(2008)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Liu, Jun-Cheng
;
Kei, Chi-Chung
This paper describes the structural and electrical properties of Al(2)O(3) thin films grown through atomic layer deposition onto Ge substrates over a wide deposition temperature range (50-300 degrees C). From grazing-incidence X-ray reflectivity and X-ray photoelectron spectroscopy, we found that increasing the deposition temperature improved the Al(2)O(3) film density and its dielectric stoichiometry; nevertheless, dielectric intermixing between main Al(2)O(3) and interfacial GeO(2) appeared at temperatures above 200 degrees C, along with degradation of the GeO(2)/Ge interface. Accordingly, a relatively large gate leakage current (J(g)) and a high density of interfacial states D(it) (> 10(13) cm(-2) eV(-1)) were observed as a result of deterioration of the entire Al(2)O(3)/Ge structure at higher deposition temperatures. In addition, although subsequent high-temperature processing at 600 degrees C in a N(2) ambient could relieve the oxygen-excessive behavior further, i.e., to provide a more stoichiometric film, the accompanying GeO(x) volatilization close to the dielectric interface caused greater damage to the electrical performance. Only forming gas annealing (H(2)/N(2), 1:10) at low temperature (300 degrees C) improved the capacitance-voltage characteristics of the Pt/Al(2)O(3)/Ge structure, in terms of providing a lower value of D(it) (ca. 6 x 10(11) cm(-2) eV(-1)), a lower value of J(g), and a reduced hysteresis width.
Effect of Low Temperature Ge Seed Layer and Post Thermal Annealing on Quality of Ge1-xSix (0.05 <= x <= 0.1) Graded Buffer Layers by UHV-CVD
(2014-07-01)
Chi-Lang Nguyen
;
Nguyen Hong Quan
;
Binh-Tinh Tran
;
Su, Yung-Hsuan
;
Tang, Shih-Hsuan
High crystal quality, smooth surface and fully relaxed Ge1-xSix (0.05 <= x <= 0.1) buffers are grown on 6 degrees-off (100) Si substrate by UHV-CVD. A low-temperature (LT) Ge seed layer is used to improve the quality of the Ge1-xSix buffers. In this study, the LT-Ge seed layer is deposited directly onto the Si substrate at a low temperature of 315 degrees C. After that, stress-free Si0.1Ge0.9 and Si0.05Ge0.95 layers are grown, respectively. An in-situ annealing process is also performed for the Si0.1Ge0.9/LT-Ge layers to increase the degree of relaxation. The total thickness of the epitaxial layer is 270 nm, with the average surface roughness at 0.6 nm.
Effects of interfacial sulfidization and thermal annealing on the electrical properties of an atomic-layer-deposited Al(2)O(3) gate dielectric on GaAs substrate
(2008-04-01)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Yang, Chun-Hui
;
Chang, Ching-Chih
In this study we investigated the interfacial chemistry occurring between an atomic-layer-deposited Al(2)O(3) high-k film and a GaAs substrate and the impact of sulfidization and thermal annealing on the properties of the resultant capacitor. We observed that sulfide passivation of the Al(2)O(3)/GaAs structure improved the effect of Fermi level pinning on the electrical characteristics, thereby providing a higher oxide capacitance, smaller frequency dispersion, and reduced surface states, as well as decreased interfacial charge trapping and gate leakage currents. Photoemission analysis indicated that the (NH(4))(2)S-treated GaAs improved the quality of the as-deposited Al(2)O(3) thin film and preserved the stoichiometry of the dielectric during subsequent high-temperature annealing. This behavior was closely correlated to the diminution of GaAs native oxides and elemental arsenic defects and their unwanted diffusion. In addition, thermal processing under an O(2) atmosphere, relative to that under N(2), decreased the thickness of the Al(2)O(3) gate dielectric and relieved the gate leakage degradation induced by metallic arsenic; as a result, superior dielectric reliability was attained. We discuss the underlying thermochemical reactions that account for these experimental observations. (C) 2008 American Institute of Physics.
Effects of Minority-Carrier Response Behavior on Ge MOS Capacitor Characteristics: Experimental Measurements and Theoretical Simulations
(2009-05-01)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
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Luo, Guang-Li
;
Ling, Yu-Ting
;
Chang, Ruey-Dar
In this paper, we present MEDICI simulations of the admittance-voltage properties of Ge and Si MOS devices, including analyses of substrate conductance Grub and high-low transition frequency f(tran), to explore the differences in the minority-carrier response. The Arrhenius-dependent G(sub) characteristics revealed that a larger energy loss-by at least four orders of magnitude-occurs in Ge than in Si, reflecting the fast minority-carrier response rate, i.e., a higher value of f(tran). We confirmed that the higher intrinsic carrier concentration in Ge, through the generation/recombination of midgap trap levels as well as the diffusion mechanism, resulted in the onset of low-frequency C-V curves in the kilohertz regime, accompanying the gate-independent inversion conductance. The experimental data obtained from Al(2)O(3)/Ge MOS capacitors were consistent with the values of G(sub) and f(tran) obtained from MEDICI predictions and theoretical calculations. In addition, upon increasing the inversion biases, we observed shifts in the G(sub/)f conductance peaks to low frequencies that mainly arose from the transition of minority carriers with bulk traps in the depletion layer. Meanwhile, we estimated that the bulky defects of ca. (2-4) x 10(15) cm(-3) exist in present-day low-doped Ge wafers.
Electrical and material characterization of atomic-layer-deposited Al(2)O(3) gate dielectric on ammonium sulfide treated GaAs substrates
(2008)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Chang, Ching-Chih
;
Kei, Chi-Chung
This paper has studied the electrical and interfacial properties of atomic-layerdeposited Al(2)O(3) thin film on ammonium-sulfide passivated GaAs. It was found that the Al(2)O(3) deposited at 300 degrees C relative to that at 100 degrees C showed the nearly four orders of magnitude reduction in gate leakage current at the capacitance-equivalent-thickness of 40 angstrom. The capacitance-voltage (C-V) characteristics displayed the higher oxide capacitance, reduced frequency dispersion and less charge trapping when GaAs receiving (NH(4))(2)S sulfide immersion; these improvements can be reasonably explained by the suppression of both native oxides and the resultant improved interface quality. Annealing as-deposited Al(2)O(3)/GaAs structures at high temperatures further reduces the Fermi level pinning effect on accumulation capacitance, however, causes an increase in C-V frequency dispersion and gate leakage current. We suggested that these phenomena are strongly associated to the amount of As-related defects resided at the dielectric/ substrate interface during thermal desorption.
Enhancing the Performance of Germanium Channel nMOSFET Using Phosphorus Dopant Segregation
(2014-01-01)
Chen, Che-Wei
;
Tzeng, Ju-Yuan
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Chung, Cheng-Ting
;
Chien, Hung-Pin
;
Chien, Chao-Hsin
In this letter, we present a high performance Ge n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a NiGe Schottky junction source/drain fabricated using phosphorus dopant segregation. Phosphorus atoms were implanted into NiGe and then driven toward the NiGe/p-Ge interface to depin the Fermi level and form a Schottky junction. A high effective barrier height (Phi(Bp)) of 0.57 eV, resulting in a high junction current ratio of >10(4) at the applied voltage vertical bar V-a vertical bar = +/- 1 V. The nMOSFET exhibited a high I-ON/I-OFF ratio of similar to 8 x 10(3) (I-D), similar to 10(5) (I-S), and a subthreshold swing of 138 mV/decade. The nMOSFET developed in this letter exhibited greater transconductance and a drain leakage current that is more than two orders of magnitude lower compared with nMOSFETs with the conventional n(+)/p junction.
Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High I-ON/I-OFF Ratio Ge FinFETs
(2013-06-01)
Chung, Cheng-Ting
;
Chen, Che-Wei
;
Lin, Jyun-Chih
;
Wu, Che-Chen
;
Chien, Chao-Hsin
Integrating germanium (Ge) thin film on silicon-on-insulator (SOI) substrate and fabricating Ge fin field-effect transistors (FinFETs) are demonstrated in this paper. Directly grown Ge film on a high-resistivity thin SOI substrate provides a good platform for fabricating advanced Ge devices. The SOI structure could effectively suppress junction leakage; therefore, high I-ON/I-OFF ratio (similar to 5 x 10(5), at V-D = 0.1 V) of the drain current is achieved. Tri-gate structure provides better short-channel control abilities for the Ge FinFETs, and the drain-induced barrier lowering and threshold voltage (V-TH) shift can be maintained at the level of similar to 110 mV/V and similar to 0.1 V, respectively, for Ge n-channel FinFET with L-channel = 120 nm and W-Fin = 40 nm. Multifin Ge FinFET with L-channel = 170 nm and W-Fin = 50 nm is also illustrated. Both N-and P-FinFETs possess high I-ON/I-OFF ratio over 104. Besides, the subthreshold swing could be reduced around 25% after forming gas annealing.
Experimental Demonstration of (111)-Oriented GaAs Metal-Oxide-Semiconductor Field-Effect-Transistors with Hetero-Epitaxial Ge Source/Drain
(2014)
Han, Tsung-Yu
;
Luo, Guang-Li
;
Cheng, Chao-Ching
;
Ko, Chih-Hsin
;
Wann, Clement H.
We demonstrate source/drain (S/D) design for GaAs n-type metal-oxide-semiconductor field-effect transistor (NMOSFET) by embedding Ge into recessed S/D region to eliminate the intrinsic issues of the low solid solubility of dopants and low density of states (DOS) in GaAs material. For achieving high quality S/D epitaxy, the effects of substrate orientation and surface preparation on the quality of the epitaxial Ge film were investigated. High quality Ge film was successfully grown on the GaAs (111)A substrate by using a ultra high vacuum chemical vapor deposition (UHVCVD) tool and the significant improvement in the surface root-mean-square (RMS) roughness was observed as compared to that on the (100) substrate. The fabricated GaAs NMOSFET with hetero-Ge S/D exhibits an I-on/I-off ratio of similar to 2.5 x 10(2). Even though the performance can be further improved, we think our proposed scheme sheds the light on overcoming the issues of the low solid solubility of n-dopant and low DOS in III-V MOSFETs. (C) 2014 The Electrochemical Society. All rights reserved.
Experimental Realization of a Ternary-Phase Alloy Through Microwave-Activated Annealing for Ge Schottky pMOSFETs
(2016-07)
Hsu, Chung-Chun
;
Chi, Wei-Chun
;
Tsai, Yi-He
;
Chou, Chen-Han
;
Chen, Che-Wei
This paper presents a high-performance Ge p-channel MOSFET (pMOSFET) with NiGePt as a ternary-phase alloy of Schottky source/drain (S/D) formed through low-temperature microwave-activated annealing (MWA). We fabricated a NiGePt alloy contact with uniform crystallinity through structural engineering and MWA. We clarified the phenomena of thermal reaction and diffusion for forming ternary-phase alloys using MWA properties such as thermal dynamics and ionic transportation. The ternary-phase NiGePt alloy is crucial for improving the off-leakage current of the junction. A lower process temperature is beneficial for eliminating surface roughness and reducing alloy agglomeration of the Schottky contact S/D. Consequently, the fabricated NiGePt/n-Ge Schottky junction exhibited a high effective barrier height (Phi(Bn)) of 0.59 eV, resulting in a high junction current ratio of more than 10(5) at an applied voltage of vertical bar V-a vertical bar = 1 V. In addition, we exploited the advantages of low-temperature microwave annealing to fabricate the pMOSFET, which includes a GeO2 passivation layer and a Schottky S/D. Our ternary Schottky Ge pMOSFET (L = 4 mu m) exhibited high I-ON/I-OFF ratios of approximately 3.7x10(3)(I-D) and 1.3x10(5)(I-S) and a moderate subthreshold swing of 126 mV/dec.
First Experimental Ge CMOS FinFETs Directly on SOI Substrate
(2012)
Chung, Cheng-Ting
;
Chen, Che-Wei
;
Lin, Jyun-Chih
;
Wu, Che-Chen
;
Chien, Chao-Hsin
High-performance Ge CMOS FinFETs directly on thin silicon on insulator (SOI) wafer are demonstrated. For the first time, NFET of L-channel = 120nm and Fin width=40nm with high I-on/I-off ratio (>10(5)), excellent drain induced barrier lowering (DIBL) (110mV/V) and subthreshold swing (S. S) (144mV/dec) has been shown. Both Ge n- and p-channel FinFETs with multi-fins have been achieved. Even the NFET of L-channel =90nm exhibits a pretty well on-off behavior after forming gas annealing.
Five-element circuit model using linear-regression method to correct the admittance measurement of metal-oxide-semiconductor capacitor
(2009-01-01)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
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Luo, Guang-Li
;
Liu, Jun-Cheng
;
Chen, Yi-Cheng
The authors present a linear-regression method based on a five-element circuit model to correct measured capacitance-voltage and conductance-voltage curves. This model explains the effects of series resistance and parasitic capacitance/inductance on the frequency dispersion of measured capacitance and the magnification of measured conductance. These extracted parasitic components show significant dependencies on the geometry of capacitor structure, thereby causing different frequency-dependent capacitance characteristics in measurements. (C) 2009 American Vacuum Society. [DOI: 10.1116/1.3058724]
Fully Depleted GeOI-Channel Junctionless pMOSFET with a Low-Resistance-Raised NiGe Alloy S/D
(2017-01-01)
Lee, Wei-Li
;
Hsu, Chung-Chun
;
Chung, Cheng-Ting
;
Lu, Yu-Hung
;
Luo, Guang-Li
We fabricated a Ge junctionless p-channel metal-oxide-semiconductor field-effect transistor (JL pMOSFET) with a raised metal source/drain (S/D) composed of a metal alloy. An ultrathin-body Ge channel was trimmed to 10 nm, which is lower than the maximum depletion width, to completely switch off the device. The fabricated Ge JL pMOSFET containing a raised Ni/NiGe S/D exhibited a high on/off current ratio (I-on/I-off) value (approximately 10(5) at V-DS =-0.1 V). The S/D series resistance of the full metal S/D structure was exactly lower than the structures of Ge/NiGe and Ge bulk S/D. Synopsys Technology Computer-Aided Design tools were used to confirm the advantages of the full metal S/D structure and demonstrate the enhancement of the S/D resistance in a device with scaled gate length. The proposed scheme is suitable for reducing the series resistance of a device with minimized dimensions. (C) 2017 The Electrochemical Society. All rights reserved.
Ge epitaxial films on GaAs (100), (110), and (111) substrates for applications of CMOS heterostructural integrations
(2013-03-01)
Tang, Shih-Hsuan
;
Kuo, Chien-I
;
Trinh, Hai-Dang
;
Chang, Edward Yi
;
Nguyen, Hong-Quan
Epitaxial Ge films were grown on GaAs (100), (110), and (111) substrates by using ultra-high vacuum chemical vapor deposition and studied with various methods. The incubation times and growth rates were quite different for these three GaAs substrates because the surface arsenic coverage on GaAs and hydrogen desorption energy on Ge are different for each orientation. High-resolution x-ray diffraction measurements, direct band-gap emission of photoluminescence measurements, and cross-sectional transmission electron microscopy showed that the Ge films had high crystal quality, low defect density, and sharp Ge/GaAs interfaces. In this study, atomic force microscopy analysis found that the Ge films grow on GaAs (100) and (111) via the Frank van der Merwe mode, while the Ge film grows on GaAs (110) via the Volmer-Weber mode at the initial growth stage, which can be explained by the thermodynamic theory of capillarity. Interestingly, when the thickness of the Ge film on the GaAs (110) substrate increases to similar to 220 nm, the 3D Ge islands merge and form a smooth surface (rms roughness of 0.3 nm), which is useful for devices. The authors also fabricated Ge metal-oxide-semiconductor capacitors (MOSCAPs) on GaAs (100) and (110) substrates. Both Ge/GaAs (100) and Ge/GaAs (110) MOSCAPs exhibit good capacitance-voltage responses with strong inversion behaviors, which means the grown material has reached device quality. The Ge/GaAs (110) structure especially offers optimal integration of Ge pMOSFETs on GaAs substrates because Ge (110) has a high hole mobility compared with Ge (100) and (111). (C) 2013 American Vacuum Society. [http://dx.doi.org/10.1116/1.4789427]
Ge Epitaxial Growth on GaAs Substrates for Application to Ge-Source/Drain GaAs MOSFETs
(2010)
Luo, Guang-Li
;
Han, Zong-You
;
Chien, Chao-Hsin
;
Ko, Chih-Hsin
;
Wann, Clement H.
Ge films were epitaxially grown on GaAs(100) substrates and Ga(0.88)In(0.12)As(100) virtual substrates using an ultrahigh vacuum/chemical vapor deposition system. The incubation time of Ge growth depends on Ga(In)As surfaces that were processed by different wet chemical solutions. Growth behaviors, such as island growth at the initial stages and selective growth into recessed regions of GaAs, were studied by transmission electron microscopy. To test the quality of Ge grown on GaAs, an n(+)-Ge/p-GaAs diode was fabricated. We propose that through Ge selective epitaxial growth, Ge can be used as the source-drain of a GaAs metal-oxide-semiconductor field-effect transistor (MOSFET) to overcome some intrinsic limitations of this device. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3246000] All rights reserved.