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顯示 21 到 40 筆資料，總共 191 筆 < 上一頁   下一頁 >
公開日期標題作者
1-十一月-2011Effects of Channel Width and Nitride Passivation Layer on Electrical Characteristics of Polysilicon Thin-Film TransistorsLiao, Chia-Chun; Lin, Min-Chen; Chiang, Tsung-Yu; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-一月-2020Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS InverterSung, Po-Jung; Su, Chun-Jung; Lo, Shih-Hsuan; Hsueh, Fu-Kuo; Lu, Darsen D.; Lee, Yao-Jen; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
23-四月-2012Electrical and reliability characteristics of polycrystalline silicon thin-film transistors with high-kappa Eu2O3 gate dielectricsYen, Li-Chen; Hu, Chia-Wei; Chiang, Tsung-Yu; Chao, Tien-Sheng; Pan, Tung-Ming; 電子物理學系; Department of Electrophysics
2009Electrical Characteristics of High Performance SPC and MILC p-Channel LTPS-TFT with High-kappa Gate DielectricMa, Ming-Wen; Chiang, Tsung-Yu; Yeh, Chi-Ruei; Chao, Tien-Sheng; Lei, Tan-Fu; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-五月-2013Enhancement of Open-Circuit Voltage Using CF4 Plasma Treatment on Nitric Acid OxidesLin, Je-Wei; Wu, Chien-Hung; Wu, Sheng-Wei; Hseih, Wei-Ping; Du, Chen-Hsu; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
2009Enhancement of Stress-Memorization Technique on nMOSFETs by Multiple Strain-Gate EngineeringLu, Tsung Yi; Wang, Chin Meng; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-一月-2019Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm x 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free ProcessLee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; 光電工程研究所; Department of Electrophysics; Department of Photonics; Institute of EO Enginerring
1-十一月-2019Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing ProcessLee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; Department of Electrophysics; Department of Photonics
1-一月-2011Fabrication and Characterization of High-k Dielectric Nickel Titanate Thin Films Using a Modified Sol-Gel MethodChuang, Shiow-Huey; Hsieh, Min-Lung; Wu, Shih-Chieh; Lin, Hong-Cai; Chao, Tien-Sheng; Hou, Tuo-Hung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016Fabrication and Characterization of Pi-Gate Poly-Si Junctionless and Inversion Mode Fin-FETs for 3-D IC ApplicationsHsieh, Don-Ru; Lin, Jer-Yi; Kuo, Po-Yi; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-三月-2011Fabrication of sub-100-nm metal-oxide-semiconductor field-effect transistors with asymmetrical source/drain using I-line double patterning techniqueLin, Horng-Chih; Tsai, Tzu-I; Chao, Tien-Sheng; Jian, Min-Feng; Huang, Tiao-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-2020Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET InvertersSung, Po-Jung; Chang, Shu-Wei; Kao, Kuo-Hsing; Wu, Chien-Ting; Su, Chun-Jung; Cho, Ta-Chun; Hsueh, Fu-Kuo; Lee, Wen-Hsi; Lee, Yao-Jen; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
2008Fluorinated HfO2 Gate Dielectrics Engineering for CMOS by pre- and post-CF4 Plasma PassivationWu, Woei-Chemg; Lai, Chao-Sung; Lee, Shih-Ching; Ma, Ming-Wen; Chao, Tien-Sheng; Wang, Jer-Chyi; Hsu, Chih-Wei; Chou, Pai-Chi; Chen, Jian-Hao; Kao, Kuo-Hsing; Lo, Wen-Cheng; Lu, Tsung-Yi; Tay, Li-Lin; Rowell, Nelson; 電子物理學系; Department of Electrophysics
1-十月-2010Formation and Structural Characterization of Cobalt Titanate Thin FilmsChuang, Shiow-Huey; Gao, Reui-Hong; Gao, Kuo-Hsing; Chiang, Michael Y.; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
2011Formation of inverted-pyramid structure by modifying laser processing parameters and acid etching timeLin, Je-Wei; Liu, En-Ting; Wu, Chien-Hung; Hsieh, Ing-Jar; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-九月-2006Fringing electric field effect on 65-nm-node fully depleted silicon-on-insulator devicesMa, Ming-Wen; Chao, Tien-Sheng; Kao, Kuo-Hsing; Huang, Jyun-Siang; Lei, Tan-Fu; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2011Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire ChannelsSu, Chun-Jung; Tsai, Tzu-I; Liou, Yu-Ling; Lin, Zer-Ming; Lin, Horng-Chih; Chao, Tien-Sheng; 電子物理學系; 電子工程學系及電子研究所; 奈米中心; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics; Nano Facility Center
1-一月-2011High Performance Cu-doped SiO2 ReRAM by a Novel Chemical Soak MethodChin, Fun-Tat; Yang, Wen-Luh; Chao, Tien-Sheng; Chang, Yuan-Ming; Lin, Li-Min; Liu, Sheng-Hsien; Lin, Chia-Hsiung; 電子物理學系; Department of Electrophysics
2015High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs ApplicationsLee, Yao-Jen; Cho, Ta-Chun; Sung, Po-Jung; Kao, Kuo-Hsing; Hsueh, Fu-Kuo; Hou, Fu-Ju; Chen, Po-Cheng; Chen, Hsiu-Chih; Wu, Chien-Ting; Hsu, Shu-Han; Chen, Yi-Ju; Huang, Yao-Ming; Hou, Yun-Fang; Huang, Wen-Hsien; Yang, Chih-Chao; Chen, Bo-Yuan; Lin, Kun-Lin; Chen, Min-Cheng; Shen, Chang-Hong; Huang, Guo-Wei; Huang, Kun-Ping; Current, Michael I.; Li, Yiming; Samukawa, Seiji; Wu, Wen-Fa; Shieh, Jia-Min; Chao, Tien-Sheng; Yeh, Wen-Kuan; 電子物理學系; 電機學院; Department of Electrophysics; College of Electrical and Computer Engineering
2011High Tensile Stress with Minimal Dopant Diffusion by Low Temperature Microwave AnnealLee, Yao-Jen; Lu, Yu-Lun; Mu, Zheng-Chang; Hsueh, Fu-Kuo; Chao, Tien-Sheng; Wu, Ching-Yi; 電子物理學系; Department of Electrophysics
顯示 21 到 40 筆資料，總共 191 筆 < 上一頁   下一頁 >