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公開日期標題作者
2004A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DACChen, GX; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1998A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSILu, CW; Lee, CL; Chen, JE; Su, CC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2000Oscillation ring delay test for high performance microprocessorsWu, WC; Lee, CL; Wu, MS; Chen, JE; Abadir, MS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2005A scan matrix design for low power scan-based testLin, SP; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2002Structural fault based specification reduction for testing analog circuitsChang, SJ; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2003Structure-based specification-constrained test frequency generation for linear analog circuitsChang, SJ; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002A testing scheme for crosstalk faults based on the oscillation test signalWu, MS; Lee, CL; Chang, CP; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-1998A two-phase fault simulation scheme for sequential circuitsWu, WC; Lee, CL; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2004A unified approach to detecting crosstalk faults of interconnects in deep submicron VLSILi, KSM; Lee, CL; Su, CC; Chen, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 21 到 29 筆資料，總共 29 筆 < 上一頁