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Showing results 1 to 11 of 11
Issue DateTitleAuthor(s)
1-Aug-2000ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mappingHuang, JD; Jou, JY; Shen, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1996BDD based lambda set selection in Roth-Karp decomposition for LUT architectureJiang, JH; Jou, JY; Huang, JD; Wei, JS; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1998Compatible class encoding in hyper-function decomposition for FPGA synthesisJiang, JHR; Jou, JY; Huang, JD; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1995Compatible class encoding in Roth-Karp decomposition for two-output LUT architectureHuang, JD; Joy, JY; Shen, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2005Formal compliance verification of interface protocolsYang, YC; Huang, JD; Yen, CC; Shih, CH; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1996An iterative area/performance trade-off algorithm for LUT-based FPGA technology mappingHuang, JD; Jou, JY; Shen, WZ; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-Dec-1998On circuit clustering for area/delay tradeoff under capacity and pin constraintsHuang, JD; Jou, JY; Shen, WZ; Chuang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2005Stimulus generation for interface protocol verification using the non-deterministic extended finite state machine modelShih, CH; Huang, JD; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Apr-2001Unified functional decomposition via encoding for FPGA technology mappingJiang, JH; Jou, JY; Huang, JD; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Oct-1997A variable partitioning algorithm of BDD for FPGA technology mappingJiang, JH; Jou, JY; Huang, JD; Wei, JS; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
2004Verification on port connectionsLee, GW; Wang, CY; Huang, JD; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
Showing results 1 to 11 of 11