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瀏覽 的方式： 關鍵字 technology mapping

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公開日期標題作者
1-八月-2000ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mappingHuang, JD; Jou, JY; Shen, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2000Delay-optimal technology mapping for hard-wired non-homogeneous FPGAsChuang, HH; Jou, JY; Shung, CB; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十月-1996Technology mapping for FPGAs with composite logic block architecturesChuang, HH; Shung, CB; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-十月-1996Technology mapping for FPGAs with composite logic block architecturesChuang, HH; Shung, CB; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2001Unified functional decomposition via encoding for FPGA technology mappingJiang, JH; Jou, JY; Huang, JD; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007以雜號干擾最小化為目標並符合延遲條件之技術映射范芳瑜; Fang-Yu Fan; 陳宏明; Hung-Ming Chen; 電子研究所
2000複合式用戶可規劃閘陣列之技術映射莊咸和; Hsien-Ho Chuang; 周景揚; 項春申; Jing-Yang Jou; C. Bernard Shung; 電子研究所
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