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公開日期標題作者
1-一月-2009A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE SystemWong, Cheng-Chi; Lee, Yung-Yu; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE SystemWong, Cheng-Chi; Lee, Yung-Yu; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE SystemWong, Cheng-Chi; Lee, Yung-Yu; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-2013A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual TrellisLin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2015An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo DecoderLin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2010Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE SystemWong, Cheng-Chi; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 6 筆資料，總共 6 筆