A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis

Abstract

This paper presents a multiple code-rate turbo decoder using the reciprocal dual trellis to improve the hardware efficiency. For a convolutional code with code rate k/(k + 1), its corresponding reciprocal dual code with rate 1/(k + 1) has smaller codeword space than the original code while k > 1, leading to a simplified trellis of the high code-rate code. The proposed decoder architecture can decode code rate k/(k + 1) constituent convolutional codes for k = 1, 2, 4, 8, and 16. Moreover, two parallel soft-in/soft-out (SISO) decoders are exploited in our turbo decoder by using the quadratic permutation polynomial (QPP) interleaver to improve the decoding speed. After fabricated in 1P9M CMOS 40 nm process, the proposed decoder with 1.27 mm(2) core area can achieve 535 Mbps throughput at 8/9 code rate, and the energy efficiency is 0.068 nJ/bit/iteration at 0.9 V.