標題: | A Multiple Code-Rate Turbo Decoder Based on Reciprocal Dual Trellis Architecture |
作者: | Lin, Chen-Yang Wong, Cheng-Chi Chang, Hsie-Chia 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
公開日期: | 2010 |
摘要: | To increase channel efficiency for high throughput systems, the high code-rate schemes are usually required. However, conventional turbo decoders in high code-rate usually apply high radix trellis structure, and the complexity of the trellis increases exponentially according to the code-rate. In this paper, the reciprocal dual trellis is applied to reduce the trellis complexity and a multiple code-rate turbo decoder is proposed. A sign magnitude representation is also introduced to lower the hardware complexity. The puncturing methodology is applied to WCDMA system as a case study of high code-rate turbo codes, and the investigated code-rates are 1/3, 1/2, 2/3, and 4/5. The simulation results are also shown in this paper. Fabricated with CMOS 90nm process, the proposed decoder containing 370K logic gates and 58kb storage units can achieve 101Mb/s with 80mW at code-rate 4/5. |
URI: | http://hdl.handle.net/11536/26387 |
ISBN: | 978-1-4244-5309-2 |
ISSN: | 0271-4302 |
期刊: | 2010 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS |
起始頁: | 1496 |
結束頁: | 1499 |
顯示於類別: | 會議論文 |