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顯示 1 到 11 筆資料，總共 11 筆
公開日期標題作者
1-八月-2003Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC productLin, IC; Huang, CY; Chao, CJ; Ker, MD; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002Characterization and Modeling of on-chip inductor substrate coupling effectChao, CJ; Wong, SC; Hsu, CJ; Chen, MJ; Leu, LY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002Characterization and modeling of on-chip inductor substrate coupling effectChao, CJ; Wong, SC; Hsu, CJ; Chen, MJ; Leu, LY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2002Characterization and Modeling of on-chip inductor substrate coupling effectChao, CJ; Wong, SC; Hsu, CJ; Chen, MJ; Leu, LY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2002Characterization and Modeling of on-chip spiral inductors for Si RFICsChao, CJ; Wong, SC; Kao, CH; Chen, MJ; Leu, LY; Chiu, KY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2004Design optimization of ESD protection and latchup prevention for a serial I/O ICHuang, CY; Chen, WF; Chuan, SY; Chiu, FC; Tseng, JC; Lin, IC; Chao, CJ; Leu, LY; Ker, MD; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-2000An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuitsWong, SC; Lee, TGY; Ma, DJ; Chao, CJ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-1998An extraction method to determine interconnect parasitic parametersChao, CJ; Wong, SC; Chen, MJ; Liew, BK; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-1998An extraction method to determine interconnect parasitic parametersChao, CJ; Wong, SC; Chen, MJ; Liew, BK; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-1998Fuzzy pattern recognition model for diagnosing cracks in RC structuresChao, CJ; Cheng, FP; 土木工程學系; Department of Civil Engineering
2000New insights on RF CMOS stability related to bias, scaling, and temperatureSu, JG; Wong, SC; Chang, CY; Chiu, KY; Huang, TY; Ou, CT; Kao, CH; Chao, CJ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 11 筆資料，總共 11 筆