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公開日期標題作者
1-九月-2007Accurate prediction of enzyme subfamily class using an adaptive fuzzy k-nearest neighbor methodHuang, Wen-Lin; Chen, Hung-Ming; Hwang, Shiow-Fen; Ho, Shinn-Ying; 生物科技學系; 生物資訊及系統生物研究所; Department of Biological Science and Technology; Institude of Bioinformatics and Systems Biology
1-九月-2014ACER: An Agglomerative Clustering Based Electrode Addressing and Routing Algorithm for Pin-Constrained EWOD ChipsLiu, Sean Shih-Ying; Chang, Chung-Hung; Chen, Hung-Ming; Ho, Tsung-Yi; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection LinesChi, Hao-Yu; Lin, Zi-Jun; Hung, Chia-Hao; Liu, Chien-Nan Jimmy; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2013Agglomerative-Based Flip-Flop Merging and Relocation for Signal Wirelength and Clock Tree OptimizationLiu, Sean Shih-Ying; Lo, Wan-Ting; Lee, Chieh-Jui; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2012Agglomerative-Based Flip-Flop Merging with Signal Wirelength OptimizationLiu, Sean Shih-Ying; Lee, Chieh-Jui; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2018Analog Placement with Current Flow and Symmetry Constraints using PCP-SPPatyal, Abhishek; Pan, Po-Cheng; Asha, K. A.; Chen, Hung-Ming; Chi, Hao-Yu; Liu, Chien-Nan; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-一月-2013The Analysis of Nano-Patterned Sapphire Substrates-Induced Compressive Strain to Enhance Quantum-Confined Stark Effect of InGaN-Based Light-Emitting DiodesChen, Po-Hsun; Su, Vincent; You, Yao-Hong; Lee, Ming-Lun; Hsieh, Cheng-Ju; Kuan, Chieh-Hsiung; Chen, Hung-Ming; Yang, Han-Bo; Lin, Hung-Chou; Lin, Ray-Ming; Chu, Fu-Chuan; Su, Gu-Yi; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2017An Analytical Placer for Heterogeneous FPGAs via Rough-Placed PackingWu, Wan-Ning; Chen, Chen; Chin, Ching-Yu; Wang, Chun-Kai; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015An Approach to Anchoring and Placing High Performance Custom Digital DesignsLiu, Shih-Ying; Chen, Tung-Chieh; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2010Area-I/O RDL Routing for Chip-Package Codesign Considering Regional AssignmentLin, Kun-Sheng; Hsu, Hsin-Wu; Lee, Ren-Jie; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2014An Automatic Synthesis Tool for Nanometer Low Dropout Regulator Using Simulation Based Model and Geometric ProgrammingHsu, Shih-Hsin; Chen, Wei-Zen; Zheng, Jui-Pin; Liu, Sean S. -Y.; Pan, Po-Cheng; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2008Blockage and Voltage Island-Aware Dual-VDD Buffered Tree Construction Under Fixed Buffer LocationsTseng, Bruce; Chen, Hung-Ming; 交大名義發表; National Chiao Tung University
1-八月-2013Board- and Chip-Aware Package Wire PlanningLee, Ren-Jie; Hsu, Hsin-Wu; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009Buffer/Flip-Flop Block Planning for Power-Integrity-Driven FloorplanningPan, Hsin-Hua; Chen, Hung-Ming; Chang, Chia-Yi; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Characteristic fluctuation dependence on discrete dopant for 16nm SOI FinFETs at different temperatureLi, Yiming; Hwang, Chih-Hong; Yu, Shao-Ming; Huang, Hsuan-Ming; Yeh, Ta-Ching; Cheng, Hui-Wen; Chen, Hung-Ming; Hwang, Jiunn-Ren; Yang, Fu-Liang; 電信工程研究所; Institute of Communications Engineering
2011Clock Planning for Multi-Voltage and Multi-Mode DesignsTsai, Chang-Cheng; Lin, Tzu-Hen; Tsai, Shin-Han; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-2014Clock Tree Synthesis Considering Slew Effect on Supply Voltage VariationWang, Chun-Kai; Chang, Yeh-Chi; Chen, Hung-Ming; Chin, Ching-Yu; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Co-placement optimization in sensor-reusable cyber-physical digital microfluidic biochipsLi, Jian-De; Kuo, Chun-Hao; Lu, Guan-Ruei; Wang, Sying-Jyan; Li, Katherine Shu-Min; Ho, Tsung-Yi; Chen, Hung-Ming; Hu, Shiyan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012Configurable Analog Routing Methodology via Technology and Design Constraint UnificationPan, Po-Cheng; Chen, Hung-Ming; Cheng, Yi-Kan; Liu, Jill; Hu, Wei-Yi; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2014Cost-Effective Decap Selection for Beyond Die Power IntegrityChen, Yi-En; Tsai, Tu-Hsiung; Chen, Shi-Hao; Chen, Hung-Ming; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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