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公開日期標題作者
1-一月-2020Coordinated and Simultaneous Formation of Paired Ge Quantum Dots by Thermal Oxidation of Designer Poly-SiGe Spacer StructuresChen, Han-Yu; Peng, Kang-Ping; George, Thomas; Lin, Horng-Chih; Li, Pei-Wen; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Feasibility of Ge double quantum dots with high symmetry and tunability in size and inter-dot spacingPeng, Kang-Ping; Huang, Tsung-Lin; George, Thomas; Lin, Horng-Chih; Li, Pei-Wen; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015Gate-stack engineering for self-aligned Ge-gate/SiO2/SiGe-channel Insta-MOS devicesLai, Wei-Ting; Yang, Kuo-Ching; Liao, Po-Hsiang; George, Thomas; Li, Pei-Wen; 交大名義發表; National Chiao Tung University
1-十月-2018The Germanium "Halo": Visualizing Ge interstitial dynamics in nanocrystallite formationGeorge, Thomas; Huang, Tsung-Lin; Hsueh, Chui-Yu; Peng, Kang-Ping; Lin, Horng-Chih; Li, Pei-Wen; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2020Nitride-stressor and quantum-size engineering in Ge quantum-dot photoluminescence wavelength and exciton lifetimeKuo, Yu-Hong; Chiu, Shih-Hsuan; Tien, Che-Wei; Lin, Sheng-Di; Chang, Wen-Hao; George, Thomas; Lin, Horng-Chih; Li, Pei-Wen; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Self-Organized Ge Nanospherical Gate/SiO2/Si0.15Ge0.85-Nanosheet n-FETs Featuring High ON-OFF Drain Current RatioLiao, Po-Hsiang; Peng, Kang-Ping; Lin, Horng-Chih; George, Thomas; Li, Pei-Wen; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Self-organized Pairs of Ge Double Quantum Dots with Tunable Sizes and Spacings Enable Room-Temperature Operation of Qubit and Single-Electron DevicesPeng, Kang-Ping; Chen, Ching-Lun; Tang, Ying-Tsan; Kuo, David; George, Thomas; Lin, Horng-Chih; Li, Pei-Wen; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
19-五月-2015A Unique Approach to Generate Self-Aligned SiO2/Ge/SiO2/SiGe Gate-Stacking Heterostructures in a Single Fabrication StepLai, Wei-Ting; Yang, Kuo-Ching; Hsu, Ting-Chia; Liao, Po-Hsiang; George, Thomas; Li, Pei-Wen; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 8 筆資料，總共 8 筆