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顯示 1 到 7 筆資料，總共 7 筆
公開日期標題作者
1-十二月-2009Communication Synthesis for Interconnect Minimization in Multicycle Communication ArchitectureHuang, Ya-Shih; Hong, Yu-Ju; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011Layer-Aware Design Partitioning for Vertical Interconnect MinimizationHuang, Ya-Shih; Liu, Yang-Hsiang; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008A multicycle communication architecture and synthesis flow for global interconnect resource sharingHuang, Wei-Sheng; Hong, Yu-Ru; Huang, Juinn-Dar; Huang, Ya-Shih; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009Simultaneous Data Transfer Routing and Scheduling for Interconnect Minimization in Multicycle Communication ArchitectureHong, Yu-Ju; Huang, Ya-Shih; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012Thermal-Aware Logic Block Placement for 3D FPGAs Considering Lateral Heat DissipationHuang, Juinn-Dar; Huang, Ya-Shih; Hsu, Mi-Yu; Chang, Han-Yuan; 交大名義發表; National Chiao Tung University
1-八月-2015TherWare: Thermal-Aware Placement and Routing Framework for 3D FPGAs with Location-Based Heat BalanceHuang, Ya-Shih; Chang, Han-Yuan; Huang, Juinn-Dar; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015三維積體電路設計最佳化之研究黃雅詩; Huang, Ya-Shih; 黃俊達; Huang, Juinn-Dar; 電子工程學系 電子研究所
顯示 1 到 7 筆資料，總共 7 筆