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公開日期標題作者
1994ALGEBRAIC DIVISION FOR MULTILEVEL LOGIC SYNTHESIS OF MULTIVALUED LOGIC-CIRCUITSWANG, HM; LEE, CL; CHEN, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-1995AN ANALYTICAL MODEL FOR THE ABOVE-THRESHOLD CHARACTERISTICS OF POLYSILICON THIN-FILM TRANSISTORSCHERN, HN; LEE, CL; LEI, TF; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-1993BINARY PARTITION ALGORITHMS AND VLSI ARCHITECTURES FOR MEDIAN AND RANK ORDER FILTERINGLEE, CL; JEN, CW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-1992BIT-SLICED MEDIAN FILTER DESIGN BASED ON MAJORITY GATELEE, CL; JEN, CW; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1979CF4 PLASMA-ETCHING ON LINBO3LEE, CL; LU, CL; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-十月-1993CHARACTERISTICS OF POLYSILICON CONTACTED SHALLOW JUNCTION DIODE FORMED WITH A STACKED-AMORPHOUS-SILICON FILMWU, SL; LEE, CL; LEI, TF; CHANG, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-1995CHARACTERISTICS OF TOP-GATE THIN-FILM TRANSISTORS FABRICATED ON NITROGEN-IMPLANTED POLYSILICON FILMSYANG, CK; LEI, TF; LEE, CL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-1993CHARACTERIZATION OF SEMIINSULATING POLYCRYSTALLINE SILICON PREPARED BY LOW-PRESSURE CHEMICAL-VAPOR-DEPOSITIONCHAO, TS; LEE, CL; LEI, TF; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
15-八月-1992CHARACTERIZATION OF ULTRATHIN OXIDE PREPARED BY LOW-TEMPERATURE WAFER LOADING AND NITROGEN PREANNEALING BEFORE OXIDATIONWU, SL; LEE, CL; LEI, TF; LIANG, MS; 電子工程學系及電子研究所; 電控工程研究所; Department of Electronics Engineering and Institute of Electronics; Institute of Electrical and Control Engineering
7-十二月-1989CIRCUIT EXAMPLE TO DEMONSTRATE THAT FAN-OUT STEMS OF PRIMARY INPUTS MUST BE CHECKPOINTSCHEN, JE; LEE, CL; SHEN, WZ; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-六月-1994CMOS THRESHOLD GATE AND NETWORKS FOR ORDER STATISTIC FILTERINGLEE, CL; JEN, CW; 電控工程研究所; Institute of Electrical and Control Engineering
1-十月-1994THE COMBINED EFFECTS OF LOW-PRESSURE NH3-ANNEALING AND H-2 PLASMA HYDROGENATION ON POLYSILICON THIN-FILM TRANSISTORSYANG, CK; LEI, TF; LEE, CL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-1994A COMPLEMENT-BASED FAST ALGORITHM TO GENERATE UNIVERSAL TEST SETS FOR MULTIOUTPUT FUNCTIONSCHEN, BY; LEE, CL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1994COMPLETE TEST SET FOR MULTIPLE-VALUED LOGIC-NETWORKSWANG, HM; LEE, CL; CHEN, JE; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-1994CORRELATION OF POLYSILICON THIN-FILM-TRANSISTOR CHARACTERISTICS TO DEFECT STATES VIA THERMAL ANNEALINGCHERN, HN; LEE, CL; LEI, TF; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1981DEPLETION WIDTHS OF THE METAL-INSULATOR SEMICONDUCTOR (MIS) STRUCTUREJEN, CW; LEE, CL; LEI, TF; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-1995DISTRIBUTED FAULT SIMULATION FOR SEQUENTIAL-CIRCUITS BY PATTERN PARTITIONINGWU, WC; LEE, CL; CHEN, JE; LIN, WY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-1995A DOUBLE METAL STRUCTURE PT/AL/N-INP DIODEHUANG, WC; LEI, TF; LEE, CL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1980A DOUBLE POLE, DOUBLE THROW ELECTRO-OPTIC SWITCH WITH AN N-TYPE ELECTRODELEE, CL; HUANG, JY; 交大名義發表; 電控工程研究所; National Chiao Tung University; Institute of Electrical and Control Engineering
1-五月-1994THE EFFECTS OF FLUORINE PASSIVATION ON POLYSILICON THIN-FILM TRANSISTORSCHERN, HN; LEE, CL; LEI, TF; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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