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公開日期標題作者
1-五月-2006Effective electrostatic discharge protection circuit design using novel fully silicided N-MOSFETs in sub-100-nm device era.Lee, JW; Li, YM; 電信工程研究所; 友訊交大聯合研發中心; Institute of Communications Engineering; D Link NCTU Joint Res Ctr
1-四月-2004Electrostatic discharge protection under pad design for copper-low-K VLSI circuitsLee, JW; Li, YM; Chao, A; Tang, H; 友訊交大聯合研發中心; D Link NCTU Joint Res Ctr
1-八月-2001The enhancement of nitrogen incorporation in RTN2O annealed TEOS oxide fabricated on disilane-based polysilicon filmsLee, JW; Chen, WD; Lei, TF; Lee, CL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2003Growing high-performance tunneling oxide by CF4 plasma pretreatmentChang, TY; Lee, JW; Lei, TF; Lee, CL; Wen, HC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2001High reliability polyoxide fabricated by using TEOS oxide deposited on disilane polysilicon filmLee, JW; Lee, CL; Lei, TF; Lai, CS; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2003High reliability ultrathin interpolyoxynitride dielectrics prepared by N2O plasma annealingWang, JC; Lee, JW; Kuo, LT; Lei, TF; Lee, CL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-2003Highly reliable nickel silicide formation with a Zr capping layerLee, TL; Lee, JW; Lee, MC; Lei, TF; Lee, CL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-2001Improvements in both thermal stability of Ni-silicide and electrical reliability of gate oxides using a stacked polysilicon gate structureLee, JW; Lin, SX; Lei, TF; Lee, CL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2004The influence of Cr alloying on microstructures of Fe-Al-Mn-Cr alloysLee, JW; Wu, CC; Liu, TF; 材料科學與工程學系; Department of Materials Science and Engineering
1-九月-2005Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETsLi, YM; Chou, HM; Lee, JW; 電信工程研究所; 友訊交大聯合研發中心; Institute of Communications Engineering; D Link NCTU Joint Res Ctr
1-八月-2002Numerical simulation of quantum effects in high-k gate dielectric MOS structures using quantum mechanical modelsLi, YM; Lee, JW; Tang, TW; Chao, TS; Lei, TF; Sze, SM; 電子物理學系; 友訊交大聯合研發中心; Department of Electrophysics; D Link NCTU Joint Res Ctr
1-四月-2003Optimization of the anti-punch-through implant for electrostatic discharge protection circuit designLi, YM; Lee, JW; Sze, SM; 電子工程學系及電子研究所; 友訊交大聯合研發中心; Department of Electronics Engineering and Institute of Electronics; D Link NCTU Joint Res Ctr
1-七月-2005Performance and reliability of poly-Si TFTs on FSG buffer layerDe Wang, S; Chang, TY; Chien, CH; Lo, WH; Sang, JY; Lee, JW; Lei, TF; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2-二月-2001Phase transformations in an Fe-8Al-10Ni-2C alloyLee, JW; Liu, TF; 材料科學與工程學系; Department of Materials Science and Engineering
1-三月-2001Phase transformations in an Fe-8Al-30Mn-1.5Si-1.5C alloyLee, JW; Liu, TF; 材料科學與工程學系; Department of Materials Science and Engineering
1-四月-2005Quantum mechanical corrected simulation program with integrated circuit emphasis model for simulation of ultrathin oxide metal-oxide-semiconductor field effect transistor gate tunneling currentLi, YM; Yu, SM; Lee, JW; 友訊交大聯合研發中心; D Link NCTU Joint Res Ctr
2004Simulation of electrical characteristics of surrounding- and omega-shaped-gate nanowire FinFETsTang, CS; Yu, SM; Chou, HM; Lee, JW; Li, YM; 交大名義發表; National Chiao Tung University
2004A study of the threshold voltage variations for ultrathin body double gate SOI MOSFETsTang, CS; Lo, SC; Lee, JW; Tsai, JH; Li, YM; 電子物理學系; Department of Electrophysics
1-六月-2002Thin oxides grown on disilane-based polysiliconLee, JW; Lei, TF; Lee, CL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-2001Thin tunnel oxide grown on silicon substrate pretreated by CF4 plasmaLee, JW; Lei, TF; Lee, CL; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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