Effective electrostatic discharge protection circuit design using novel fully silicided N-MOSFETs in sub-100-nm device era.

Abstract

In this paper, the floating charge effect is considered in the design of new fully silicided NMOSFETs for designing electrostatic discharge (ESD) protection circuit consisting of nanodevices. According to the designed, fabricated, and studied new fully silicided ESD protection nanodevices (e.g., 90-nm CMOS devices), our investigation demonstrates that there is a significant improvement in sustaining ESD robustness than that of the conventional fully silicided device. Furthermore, it has an excellent electrical efficiency compared with that of drain-ballast resistor-tied devices. Moreover, our novel design exhibits a higher driving current and better reliability without suffering the off-state current of the fully silicided devices. Those good characteristics are especially suitable for the output buffer design in which both driving capability and ESD robustness have to be considered.