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顯示 1 到 13 筆資料，總共 13 筆
公開日期標題作者
1-一月-2020Analytical Modeling of Read-Induced SET-State Conductance Change in a Hafnium-Oxide Resistive Switching DeviceSu, Po-Cheng; Jiang, Cheng-Min; Chen, Yu-Jia; Wang, Chih-Chieh; Li, Kai-Shin; Lin, Chao-Cheng; Wang, Tahui; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2019Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD TechnologyChung, Yun-Yan; Lu, Kuan-Cheng; Cheng, Chao-Ching; Li, Ming-Yang; Lin, Chao-Ting; Li, Chi-Feng; Chen, Jyun-Hong; Lai, Tung-Yen; Li, Kai-Shin; Shieh, Jia-Min; Su, Sheng-Kai; Chiang, Hung-Li; Chen, Tzu-Chiang; Li, Lain-Jong; Wong, H-S Philip; Jian, Wen-Bin; Chien, Chao-Hsin; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
1-二月-2019Effective N-methyl-2-pyrrolidone wet cleaning for fabricating high-performance monolayer MoS2 transistorsChen, Po-Chun; Lin, Chih-Pin; Hong, Chuan-Jie; Yang, Chih-Hao; Lin, Yun-Yan; Li, Ming-Yang; Li, Lain-Jong; Yu, Tung-Yuan; Su, Chun-Jung; Li, Kai-Shin; Zhong, Yuan-Liang; Hou, Tuo-Hung; Lan, Yann-Wen; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrateCheng, Chao-Ching; Chung, Yun-Yan; Li, Ming-Yang; Lin, Chao-Ting; Li, Chi-Feng; Chen, Jyun-Hong; Lai, Tung-Yen; Li, Kai-Shin; Shieh, Jia-Min; Su, Sheng-Kai; Chiang, Hung-Li; Chen, Tzu-Chiang; Li, Lain-Jong; Wong, H-S Philip; Chien, Chao-Hsin; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2016First Fully Functionalized Monolithic 3D(+) IoT Chip with 0.5 V Light-electricity Power Management, 6.8 GHz Wireless-communication VCO, and 4-layer Vertical ReRAMHsueh, Fu-Kuo; Shen, Chang-Hong; Shieh, Jia-Min; Li, Kai-Shin; Chen, Hsiu-Chih; Huang, Wen-Hsien; Wang, Hsing-Hsiang; Yang, Chih-Chao; Hsieh, Tung-Ying; Lin, Chang-Hsien; Chen, Bo-Yuan; Shiao, Yu-Shao; Huang, Guo-Wei; Wong, Oi-Ying; Chen, Po-Hung; Yeh, Wen-Kuan; 電子工程學系及電子研究所; 生醫電子轉譯研究中心; Department of Electronics Engineering and Institute of Electronics; Biomedical Electronics Translational Research Center
1-六月-2019Improvement of ferroelectric properties in undoped hafnium oxide thin films using thermal atomic layer depositionLuo, Jun-Dao; Zhang, He-Xin; Wang, Zheng-Ying; Gu, Siang-Sheng; Yeh, Yun-Tien; Chung, Hao-Tung; Chuang, Kai-Chi; Liao, Chan-Yu; Li, Wei-Shuo; Li, Yi-Shao; Li, Kai-Shin; Lee, Min-Hung; Cheng, Huang-Chung; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2019Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETsHsueh, Fu-Kuo; Lee, Chun-Ying; Xue, Cheng-Xin; Shen, Chang-Hong; Shieh, Jia-Min; Chen, Bo-Yuan; Chiu, Yen-Cheng; Chen, Hsiu-Chih; Kao, Ming-Hsuan; Huang, Wen-Hsien; Li, Kai-Shin; Wu, Chien-Ting; Lin, Kun-Lin; Chen, Kun-Ming; Huang, Guo-Wei; Chang, Meng-Fan; Hu, Chenming; Yeh, Wen-Kuan; 交大名義發表; National Chiao Tung University
2016MOS2 U-shape MOSFET with 10 nm Channel Length and Poly-Si Source/Drain Serving as Seed for Full Wafer CVD MOS2 AvailabilityLi, Kai-Shin; Wu, Bo-Wei; Li, Lain-Jong; Li, Ming-Yang; Cheng, Chia-Chin Kevin; Hsu, Cho-Lun; Lin, Chang-Hsien; Chen, Yi-Ju; Chen, Chun-Chi; Wu, Chien-Ting; Chen, Min-Cheng; Shieh, Jia-Min; Yeh, Wen-Kuan; Chueh, Yu-Lun; Yang, Fu-Liang; Hu, Chenming; 材料科學與工程學系; Department of Materials Science and Engineering
1-一月-2018Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and FtLi, Kai-Shin; Wei, Yun-Jie; Chen, Yi-Ju; Chiu, Wen-Cheng; Chen, Hsiu-Chih; Lee, Min-Hung; Chiu, Yu-Fan; Hsueh, Fu-Kuo; Wu, Bo-Wei; Chen, Pin-Guang; Lai, Tung-Yan; Chen, Chun-Chi; Shieh, Jia-Min; Yeh, Wen-Kuan; Salahuddin, Sayeef; Hu, Chenming; 交大名義發表; National Chiao Tung University
17-四月-2020Nonvolatile molecular memory with the multilevel states based on MoS2 nanochannel field effect transistor through tuning gate voltage to control molecular configurationsLan, Yann-Wen; Hong, Chuan-Jie; Chen, Po-Chun; Lin, Yun-Yan; Yang, Chih-Hao; Chu, Chia-Jung; Li, Ming-Yang; Li, Lain-Jong; Su, Chun-Jung; Wu, Bo-Wei; Hou, Tuo-Hung; Li, Kai-Shin; Zhong, Yuan-Liang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2016A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FETTang, Ying-Tsan; Li, Kai-Shin; Li, Lain-Jong; Li, Ming-Yang; Lin, Chang-Hsien; Chen, Yi-Ju; Chen, Chun-Chi; Su, Chuan-Jung; Wu, Bo-Wei; Wu, Cheng-San; Chen, Min-Cheng; Shieh, Jia-Min; Yeh, Wen-Kuan; Su, Po-Cheng; Wang, Tahui; Yang, Fu-Liang; Hu, Chenming; 電機工程學系; Department of Electrical and Computer Engineering
1-一月-2009Superconductivity-induced magnetoresistance suppression in hybrid superconductor/magnetic tunnel junctionsChang, Yin-Ming; Li, Kai-Shin; Chiang, Wen-Chung; Lin, Jiunn-Yuan; Lin, Minn-Tsong; 物理研究所; Institute of Physics
2015TMD FinFET with 4 nm Thin Body and Back Gate Control for Future Low Power TechnologyChen, Min-Cheng; Li, Kai-Shin; Li, Lain-Jong; Lu, Ang-Yu; Li, Ming-Yang; Chang, Yung-Huang; Lin, Chang-Hsien; Chen, Yi-Ju; Hou, Yun-Fang; Chen, Chun-Chi; Wu, Bo-Wei; Wu, Cheng-San; Yang, Ivy; Lee, Yao-Jen; Shieh, Jia-Min; Yeh, Wen-Kuan; Shih, Jyun-Hong; Su, Po-Cheng; Sachid, Angada B.; Wang, Tahui; Yang, Fu-Liang; Hu, Chenming; 電子物理學系; 電子工程學系及電子研究所; Department of Electrophysics; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 13 筆資料，總共 13 筆