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公開日期標題作者
1-一月-2016Cellular Automata Based Hardware Accelerator for Parallel Maze RoutingSaurabh, Shashank; Lin, Kuen-Wey; Li, Yih-Lang; 資訊工程學系; Department of Computer Science
1-一月-2017Clock Tree Aware Post-Global Placement OptimizationSu, Hong-Yan; Chiang, Po-Ting; Samanta, Radhamanjari; Li, Yih-Lang; 資訊工程學系; Department of Computer Science
2009Critical-Trunk Based Obstacle-Avoiding Rectilinear Steiner Tree Routings for Delay and Slack OptimizationLin, Yen-Hung; Chang, Shu-Hsin; Li, Yih-Lang; 資訊工程學系; Department of Computer Science
1-九月-2011Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack OptimizationLin, Yen-Hung; Chang, Shu-Hsin; Li, Yih-Lang; 交大名義發表; National Chiao Tung University
1-一月-2019DATC RDF-2019: Towards a Complete Academic Reference Design FlowChen, Jianli; Jiang, Iris Hui-Ru; Jung, Jinwook; Kahng, Andrew B.; Kravets, Victor N.; Li, Yih-Lang; Lin, Shih-Ting; Woo, Mingyu; 交大名義發表; National Chiao Tung University
1-一月-2018DATC RDF: An Academic Flow from Logic Synthesis to Detailed RoutingJung, Jinwook; Jiang, Iris Hui-Ru; Chen, Jianli; Lin, Shih-Ting; Li, Yih-Lang; Kravets, Victor N.; Nam, Gi-Joon; 交大名義發表; National Chiao Tung University
1-一月-2017DATC RDF: Robust Design Flow DatabaseJung, Jinwook; Lee, Pei-Yu; Wu, Yan-Shiun; Darav, Nima Karimpour; Jiang, Iris Hui-Ru; Kravets, Victor N.; Behjat, Laleh; Li, Yih-Lang; Nam, Gi-Joon; 交大名義發表; National Chiao Tung University
2010Dead Via Minimization by Simultaneous Routing and Redundant Via InsertionLin, Chih-Ta; Lin, Yen-Hung; Su, Guan-Chan; Li, Yih-Lang; 資訊工程學系; Department of Computer Science
15-十二月-2008Design optimization of a current mirror amplifier integrated circuit using a computational statistics techniqueLi, Yiming; Li, Yih-Lang; Yu, Shao-Ming; 資訊工程學系; 電信工程研究所; Department of Computer Science; Institute of Communications Engineering
2011DOPPLER: DPL-aware and OPC-friendly Gridless Detailed Routing with Mask Density BalancingLin, Yen-Hung; Ban, Yong-Chan; Pan, David Z.; Li, Yih-Lang; 資訊工程學系; Department of Computer Science
1-一月-2010Double Patterning Lithography Aware Gridless Detailed Routing with Innovative Conflict GraphLin, Yen-Hung; Li, Yih-Lang; 資訊工程學系; Department of Computer Science
2009Efficient Simulated Evolution Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global RoutingDai, Ke-Ren; Liu, Wen-Hao; Li, Yih-Lang; 資訊工程學系; Department of Computer Science
1-二月-2007An efficient tile-based ECO router using routing graph reduction and enhanced global routing flowLi, Yih-Lang; Li, Jin-Yih; Chen, Wen-Bin; 資訊工程學系; Department of Computer Science
15-十二月-2008Electronic design automation using a unified optimization frameworkLi, Yiming; Yu, Shao-Ming; Li, Yih-Lang; 資訊工程學系; 電信工程研究所; Department of Computer Science; Institute of Communications Engineering
1-五月-2018Fast and Accurate Emissivity and Absolute Temperature Maps Measurement for Integrated CircuitsYu, Hsueh-Ling; Li, Yih-Lang; Liao, Tzu-Yi; Wang, Tianchen; Tsai, Shu-Fei; Shi, Yiyu; 資訊工程學系; Department of Computer Science
2014Fast and Accurate Emissivity and Absolute Temperature Maps Measurement for Integrated CircuitsYu, Hsueh-Ling; Li, Yih-Lang; Liao, Tzu-Yi; Wang, Tianchen; Shi, Yiyu; Tsai, Shu-Fei; 資訊工程學系; Department of Computer Science
2012A Fast Maze-Free Routing Congestion Estimator With Hybrid Unilateral Monotonic RoutingLiu, Wen-Hao; Li, Yih-Lang; Koh, Cheng-Kok; 資訊工程學系; Department of Computer Science
2010GPU平台下的高度平行化繞線演算法與其應用羅勻鍵; Lo, Yun-Jian; 李毅郎; Li, Yih-Lang; 資訊科學與工程研究所
1-三月-2011A Gridless Routing System with Nonslicing Floorplanning-Based Crosstalk Reduction on Gridless Track AssignmentLi, Yih-Lang; Chang, Yu-Ning; Cheng, Wen-Nai; 資訊工程學系; Department of Computer Science
2011Gridless Wire Ordering, Sizing and Spacing with Critical Area MinimizationLee, Yu-Wei; Lin, Yen-Hung; Li, Yih-Lang; 資訊工程學系; Department of Computer Science
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