瀏覽 的方式: 作者 Liu, CNJ

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公開日期標題作者
1-七月-2000An automatic controller extractor for HDL descriptions at the RTLLiu, CNJ; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001Automatic functional vector generation using the interacting FSM modelLiu, CNJ; Yen, CC; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2003A design-for-verification technique for functional pattern reductionLiu, CNJ; Chen, IL; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002Effective error diagnosis for RTL designs in HDLSJiang, TY; Liu, CNJ; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001An efficient design-for-verification technique for HDLsLiu, CNJ; Chen, IL; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2003An efficient IP-Level power model for complex digital circuitsHsu, CY; Liu, CNJ; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-八月-2003An efficient power model for IP-level complex designsHsu, CY; Liu, CNJ; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-2004Efficient vector compaction methods for power estimation with consecutive sampling techniquesHsu, CY; Liu, CNJ; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2005Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designsJiang, TY; Liu, CNJ; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2003Improved vector compaction for power estimation with multi-sequence sampling techniqueHsu, CY; Liu, CNJ; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2000A novel approach for functional coverage measurement in HDLLiu, CNJ; Chang, CY; Jou, JY; Lai, MC; Juan, HM; 交大名義發表; National Chiao Tung University