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公開日期標題作者
1-十二月-1991A 30-MHZ TRELLIS CODEC CHIP FOR PARTIAL-RESPONSE CHANNELSSHUNG, CB; SIEGEL, PH; THAPAR, HK; KARABED, R; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-1993AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .1. THEORYSHUNG, CB; LIN, HD; CYPHER, R; SIEGEL, PH; THAPAR, HK; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-五月-1993AREA-EFFICIENT ARCHITECTURES FOR THE VITERBI ALGORITHM .2. APPLICATIONSSHUNG, CB; LIN, HD; CYPHER, R; SIEGEL, PH; THAPAR, HK; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1994FAULT-TOLERANT ARCHITECTURES FOR SHARED BUFFER MEMORY SWITCHLIN, YF; SHUNG, CB; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-1993GENERALIZED TRACE-BACK TECHNIQUES FOR SURVIVOR MEMORY MANAGEMENT IN THE VITERBI ALGORITHMCYPHER, R; SHUNG, CB; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1994A HIGH SPEED REED-SOLOMON CODEC CHIP USING LOOKFORWARD ARCHITECTURECHANG, JY; SHUNG, CB; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-1991AN INTEGRATED CAD SYSTEM FOR ALGORITHM-SPECIFIC IC DESIGNSHUNG, CB; JAIN, R; RIMEY, K; WANG, E; SRIVASTAVA, MB; RICHARDS, BC; LETTANG, E; AZIM, SK; THON, L; HILFINGER, PN; RABAEY, JM; BRODERSEN, RW; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-1993REAL-TIME RECORDING RESULTS FOR A TRELLIS-CODED PARTIAL-RESPONSE (TCPR) SYSTEMTHAPAR, HK; SHUNG, CB; RAE, JW; KARABED, R; SIEGEL, PH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-1995SHARED BUFFER ATM SWITCH WITH DOUBLY LINKED LISTSLIN, YF; SHUNG, CB; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 9 筆資料，總共 9 筆