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公開日期標題作者
1-二月-2020Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETsLee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; 光電工程研究所; Department of Electrophysics; Department of Photonics; Institute of EO Enginerring
1-一月-2019Experimental Demonstration of Performance Enhancement of MFMIS and MFIS for 5-nm x 12.5-nm Poly-Si Nanowire Gate-All-Around Negative Capacitance FETs Featuring Seed-Layer and PMA-Free ProcessLee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; 光電工程研究所; Department of Electrophysics; Department of Photonics; Institute of EO Enginerring
1-十一月-2019Experimental Demonstration of Stacked Gate- All-Around Poly-Si Nanowires Negative Capacitance FETs With Internal Gate Featuring Seed Layer and Free of Post-Metal Annealing ProcessLee, Shen-Yang; Chen, Han-Wei; Shen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Huang, Yu-En; Chen, Hsin-Yu; Chao, Tien-Sheng; 電子物理學系; 光電工程學系; Department of Electrophysics; Department of Photonics
1-四月-2018Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs With RTA-Improved CrystallinityShen, Chiuan-Huei; Kuo, Po-Yi; Chung, Chun-Chih; Lee, Sen-Yang; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-九月-2018Variable-Channel Junctionless Poly-Si FETs: Demonstration and Investigation With Different Body Doping ConcentrationsLin, Jer-Yi; Tsai, Chan-Yi; Shen, Chiuan-Huei; Chung, Chun-Chih; Kumar, Malkundi Puttaveerappa Vijay; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
1-二月-2018Vertically Stacked Cantilever n-Type Poly-Si Junctionless Nanowire Transistor and Its Series Resistance LimitChung, Chris Chun-Chih; Shen, Chiuan-Huei; Lin, Jer-Yi; Chin, Chun-Chieh; Chao, Tien-Sheng; 電子物理學系; Department of Electrophysics
顯示 1 到 6 筆資料，總共 6 筆