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公開日期標題作者
1-八月-2000ALTO: An iterative area/performance tradeoff algorithm for LUT-based FPGA technology mappingHuang, JD; Jou, JY; Shen, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1996CB-Power: A hierarchical cell-based power characterization and estimation environment for static CMOS circuitsShen, WZ; Lin, JY; Lu, JM; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-十月-1997CB-power: A hierarchical power analysis and characterization environment of cell-based CMOS circuitsShen, WZ; Lin, JY; Lu, JM; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-二月-1998Combinative motion estimation algorithm and the corresponding architecture for complex motion phenomenonLiu, PC; Chang, WT; Shen, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1995Compatible class encoding in Roth-Karp decomposition for two-output LUT architectureHuang, JD; Joy, JY; Shen, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-1996Design and performance evaluation of a distributed knockout switch with input and output buffersCheng, YJ; Lee, TH; Shen, WZ; 電子工程學系及電子研究所; 電信工程研究所; Department of Electronics Engineering and Institute of Electronics; Institute of Communications Engineering
1-六月-1996Design and performance evaluation of a distributed knockout switch with input and output buffersCheng, YJ; Lee, TH; Shen, WZ; 電子工程學系及電子研究所; 電信工程研究所; Department of Electronics Engineering and Institute of Electronics; Institute of Communications Engineering
1-八月-1998Fault diagnosis of a distributed knockout switchCheng, YJ; Lee, TH; Shen, WZ; 電子工程學系及電子研究所; 電信工程研究所; Department of Electronics Engineering and Institute of Electronics; Institute of Communications Engineering
1-四月-2003Inductance modeling for on-chip interconnectsTu, SW; Shen, WZ; Chang, YW; Chen, TC; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2002Inductance modeling for on-chip interconnectsTu, SW; Shen, WZ; Chang, YW; Chen, TC; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1996An iterative area/performance trade-off algorithm for LUT-based FPGA technology mappingHuang, JD; Jou, JY; Shen, WZ; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-十一月-1997Motion parameter estimation based on the block recursive algorithm with finite word lengthLiu, PC; Chang, WT; Shen, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-1997Motion parameter estimation based on the block recursive algorithm with finite word lengthLiu, PC; Chang, WT; Shen, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-2000A new method for constructing IP level power model based on power sensitivityHuang, HL; Lin, JY; Shen, WZ; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十二月-1998On circuit clustering for area/delay tradeoff under capacity and pin constraintsHuang, JD; Jou, JY; Shen, WZ; Chuang, HH; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1997A power modeling and characterization method for macrocells using structure informationLin, JY; Shen, WZ; Jou, JY; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1996A power modeling and characterization method for the CMOS standard cell libraryLin, JY; Shen, WZ; Jou, JY; 交大名義發表; 電子工程學系及電子研究所; National Chiao Tung University; Department of Electronics Engineering and Institute of Electronics
1-二月-1998Recursive minimum energy algorithm for image interpolationLiu, PC; Chang, WT; Shen, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-1998Recursive minimum energy algorithm for image interpolationLiu, PC; Chang, WT; Shen, WZ; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-1999A structure-oriented power modeling technique for macrocellsLin, JY; Shen, WZ; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
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