1. 目前位置：

瀏覽 的方式： 作者 Shih, Yen-Hao

跳到： 0-9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
或是輸入前幾個字：  
顯示 1 到 4 筆資料，總共 4 筆
公開日期標題作者
1-六月-2014Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory DevicesHsiao, Yi-Hsuan; Lue, Hang-Ting; Chen, Wei-Chen; Chang, Kuo-Pin; Shih, Yen-Hao; Tsui, Bing-Yue; Hsieh, Kuang-Yeu; Lu, Chih-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2012Modeling the Variability Caused by Random Grain Boundary and Trap-location Induced Asymmetrical Read Behavior for a Tight-pitch Vertical Gate 3D NAND Flash Memory Using Double-Gate Thin-Film Transistor (TFT) DeviceHsiao, Yi-Hsuan; Lue, Hang-Ting; Chen, Wei-Chen; Chen, Chih-Ping; Chang, Kuo-Ping; Shih, Yen-Hao; Tsui, Bing-Yue; Lu, Chih-Yuan; 交大名義發表; National Chiao Tung University
2015A Study of Blocking and Tunnel Oxide Engineering on Double-Trapping (DT) BE-SONOS PerformanceLo, Roger; Du, Pei-Ying; Hsu, Tzu-Hsuan; Wu, Chen-Jun; Guo, Jung-Yi; Cheng, Chun-Min; Lue, Hang-Ting; Shih, Yen-Hao; Hou, Tuo-Hung; Hsieh, Kuang-Yeu; Lu, Chih-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2010Tungsten Oxide Resistive Memory Using Rapid Thermal Oxidation of Tungsten PlugsLai, Erh-Kun; Chien, Wei-Chih; Chen, Yi-Chou; Hong, Tian-Jue; Lin, Yu-Yu; Chang, Kuo-Pin; Yao, Yeong-Der; Lin, Pang; Horng, Sheng-Fu; Gong, Jeng; Tsai, Shih-Chang; Lee, Ching-Hsiung; Hsieh, Sheng-Hui; Chen, Chun-Fu; Shih, Yen-Hao; Hsieh, Kuang-Yeu; Liu, Rich; Lu, Chih-Yuan; 材料科學與工程學系; Department of Materials Science and Engineering
顯示 1 到 4 筆資料，總共 4 筆