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公開日期標題作者
1-三月-2015A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter SuppressionSu, Ming-Chiuan; Chen, Wei-Zen; Wu, Pei-Si; Chen, Yu-Hsiang; Lee, Chao-Cheng; Jou, Shyh-Jye; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2013A 10Gbps, 1.24pJ/bit, Burst-Mode Clock and Data Recovery with Jitter SuppressionSu, Ming-Chiuan; Chen, Wei-Zen; Wu, Pei-Si; Chen, Yu-Hsian; Lee, Chao-Cheng; Jou, Shyh-Jye; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2015A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase OutputsSu, Ming-Chiuan; Jou, Shyh-Jye; Chen, Wei-Zen; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2016A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression TechniquesChang, Chia-Wen; Lo, Kai-Yu; Ibrahim, Hossameldin A.; Su, Ming-Chiuan; Chu, Yuan-Hua; Jou, Shyh-Jye; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015應用於序列傳輸系統之突發式時脈資料回復電路與全數位式展頻時脈產生器蘇明銓; Su, Ming-Chiuan; 周世傑; 陳巍仁; Jou, Shyh-Jye; Chen, Wei-Zen; 電子工程學系 電子研究所
2009適用於展頻時脈產生器之全數位鎖相迴路蘇明銓; Su, Ming-Chiuan; 周世傑; Jou, Shyh-Jye; 電子研究所
顯示 1 到 6 筆資料，總共 6 筆