瀏覽 的方式： 作者 Tsai, Chi-Lun
顯示 1 到 3 筆資料，總共 3 筆
| 公開日期 | 標題 | 作者 |
| 2013 | Variation-Aware and Adaptive-Latency Accesses for Reliable Low Voltage Caches | Wang, Po-Hao; Cheng, Wei-Chung; Yu, Yung-Hui; Kao, Tang-Chieh; Tsai, Chi-Lun; Chang, Pei-Yao; Lin, Tay-Jyi; Wang, Jinn-Shyan; Chen, Tien-Fu; 資訊工程學系; Department of Computer Science |
| 十月-2016 | Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations | Wang, Po-Hao; Cheng, Wei-Chung; Yu, Yung-Hui; Kao, Tang-Chieh; Tsai, Chi-Lun; Chang, Pei-Yao; Lin, Tay-Jyi; Wang, Jinn-Shyan; Chen, Tien-Fu; 資訊工程學系; Department of Computer Science |
| 2013 | 適用於低電壓處理器之細細粒度列合併快取記憶體以降低時序差異 | 蔡奇倫; Tsai, Chi-Lun; 陳添福; 資訊科學與工程研究所 |
