瀏覽 的方式： 作者 Tsai, Shang-Jen
顯示 1 到 4 筆資料，總共 4 筆
| 公開日期 | 標題 | 作者 |
| 六月-2016 | Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors | Wang, Po-Hao; Tsai, Shang-Jen; Tanjung, Rizal; Lin, Tay-Jyi; Wang, Jinn-Shyan; Chen, Tien-Fu; 資訊工程學系; Department of Computer Science |
| 2015 | A Latency-Elastic and Fault-Tolerant Cache for Improving Performance and Reliability on Low Voltage Operation | Yu, Yung-Hui; Wang, Po-Han; Tsai, Shang-Jen; Chen, Tien-Fu; 資訊工程學系; Department of Computer Science |
| 1-十二月-2017 | ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures | Wang, Po-Hao; Chien, Yung-Chen; Tsai, Shang-Jen; Lin, Xuan-Yu; Tanjung, Rizal; Lin, Yi-Sian; Syu, Shu-Wei; Lin, Tay-Jyi; Wang, Jinn-Shyan; Chen, Tien-Fu; 資訊工程學系; Department of Computer Science |
| 2015 | 用於非對稱式處理器系統之可同盟字元線快取記憶體以暫時性效能提升 | 蔡上仁; Tsai, Shang-Jen; 陳添福; Chen, Tien-Fu; 資訊科學與工程研究所 |
