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公開日期標題作者
1-一月-2003Automatic interconnection rectification for SoC design verification based on the port order fault modelWang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2003An automatic interconnection rectification technique for SoC design integrationWang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十月-2002An automorphic approach to verification pattern generation for SoC design verification using port-order fault modelWang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001An improved AVPG algorithm for SoC design verification using port order fault modelWang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-九月-1998A logical fault model for library coherence checkingTung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-四月-2002On automatic-verification pattern generation for SoC with port-order fault modelWang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2001On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault modelWang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2003SOC design integration by using automatic interconnection rectificationWang, CY; Tung, SW; Jou, JY; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
顯示 1 到 8 筆資料，總共 8 筆