國立陽明交通大學機構典藏：瀏覽交通大學機構典藏

瀏覽的方式：作者 Wang, Chang-Tzu

顯示 1 到 11 筆資料，總共 11 筆

公開日期	標題	作者
2009	Circuit Solutions on ESD Protection Design for Mixed-Voltage I/O Buffers in Nanoscale CMOS	Ker, Ming-Dou; Wang, Chang-Tzu; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2010	Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology	Wang, Chang-Tzu; Ker, Ming-Dou; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-三月-2009	Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes	Ker, Ming-Dou; Wang, Chang-Tzu; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007	Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes	Ker, Ming-Dou; Wang, Chang-Tzu; Tang, Tien-Hao; Su, Kuan-Cbeng; 電機學院; College of Electrical and Computer Engineering
1-三月-2009	Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology	Wang, Chang-Tzu; Ker, Ming-Dou; 電機學院; College of Electrical and Computer Engineering
10-六月-2010	ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND RELATED CIRCUIT	Ker, Ming-Dou; Hsiao, Yuan-Wen; Wang, Chang-Tzu
13-五月-2010	ESD PROTECTION CIRCUITRY WITH MULTI-FINGER SCRS	Ker, Ming-Dou; Lin, Chun-Yu; Wang, Chang-Tzu
1-十二月-2010	ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology	Wang, Chang-Tzu; Ker, Ming-Dou; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009	Low-Leakage Electrostatic Discharge Protection Circuit in 65-nm Fully-Silicided CMOS Technology	Wang, Chang-Tzu; Ker, Ming-Dou; Tang, Tien-Hao; Su, Kuan-Cheng; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
16-七月-2009	SILICON CONTROLLED RECTIFIER	Ker, Ming-Dou; Lin, Chun-Yu; Wang, Chang-Tzu
2009	積體電路電源線間具低漏電流之靜電放電防護電路設計	王暢資; Wang, Chang-Tzu; 柯明道; Ker, Ming-Dou; 電子研究所

顯示 1 到 11 筆資料，總共 11 筆