| 標題: | Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes |
| 作者: | Ker, Ming-Dou Wang, Chang-Tzu Tang, Tien-Hao Su, Kuan-Cbeng 電機學院 College of Electrical and Computer Engineering |
| 公開日期: | 2007 |
| 摘要: | A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1xVDD devices for 3xVDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-mu m CMOS process with only 1.2-V devices. |
| URI: | http://hdl.handle.net/11536/11412 http://dx.doi.org/10.1109/RELPHY.2007.369967 |
| ISBN: | 978-1-4244-0918-1 |
| DOI: | 10.1109/RELPHY.2007.369967 |
| 期刊: | 2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL |
| 起始頁: | 594 |
| 結束頁: | 595 |
| Appears in Collections: | Conferences Paper |
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- Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes / Chang, Rong-Kun;Ker, Ming-Dou
- New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology / Yeh, Chih-Ting;Ker, Ming-Dou
- 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Low Standby Leakage in 65-nm CMOS Process / Lin, Chun-Yu;Ker, Ming-Dou
- ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces / Chang, Wei-Jen;Ker, Ming-Dou
- HIGH-VOLTAGE TOLERANT POWER-RAIL ESD CLAMP CIRCUIT / Ker, Ming-Dou;Chen, Wen-Yi
- Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs / Chen, Shih-Hung;Ker, Ming-Dou
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