Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes

標題:	Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes
作者:	Ker, Ming-Dou Wang, Chang-Tzu Tang, Tien-Hao Su, Kuan-Cbeng 電機學院 College of Electrical and Computer Engineering
公開日期:	2007
摘要:	A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1xVDD devices for 3xVDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-mu m CMOS process with only 1.2-V devices.
URI:	http://hdl.handle.net/11536/11412 http://dx.doi.org/10.1109/RELPHY.2007.369967
ISBN:	978-1-4244-0918-1
DOI:	10.1109/RELPHY.2007.369967
期刊:	2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL
起始頁:	594
結束頁:	595
顯示於類別：	會議論文

文件中的檔案：

若為 zip 檔案，請下載檔案解壓縮後，用瀏覽器開啟資料夾中的 index.html 瀏覽全文。