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Author: search.filters.author.Guo, Jyh-Chyurn

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Now showing 1 - 10 of 31
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    SiC Strained nMOSFETs With Enhanced High- Frequency Performance and Impact on Flicker Noise and Random Telegraph Noise
    (2020-06-01)
    Guo, Jyh-Chyurn
    ;
    Chang, Chih-Shiang
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Silicon-carbon (SiC) strained nMOSFETs with sub35-nm gate length in a 40-nm CMOS technology can realize superior cutoff frequency (f(T)) up to 405 GHz, attributed to more than 20% enhancement of the mobility and transconductance. This super-400-GHz f(T) makes SiC strained nMOS an attractive high mobility device aimed at millimeter-wave (mm-wave) CMOS circuits design. However, the SiC nMOSFETs reveal a dramatic increase in flicker noise and random telegraph noise (RTN), which may cause worse phase noise and detrimental impact on CMOS oscillator stability. The complex RTN features abnormally long capture and emission time constants (tau(c) and tau(e)) and suggests electron-phonon coupling responsible for the anomalously slow trapping and detrapping, due to a significant increase of relaxation energy from SiC strain. This critical tradeoff between high-frequency performance and low-frequency noise becomes a key factor to be considered for the most appropriate adoption of high mobility devices and design optimization adapted to various circuits.
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    A New Compact Model for Accurate Simulation of RF Noise in Sub-40nm Multi-finger nMOSFETs
    (2018-01-01)
    Guo, Jyh-Chyurn
    ;
    Yeh, Kuo-Liang
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A new compact model has been developed in this paper for accurate simulation of RF noise and extraction of actual intrinsic noise in sub-40 nm multi-finger nMOSFETs. This model can predict and verify the excess noise sources before and after deembedding, the mechanism responsible for the complicated layout dependence in various noise parameters, and facilitate optimization design for low noise devices and circuits in nanoscale CMOS technology.
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    New Observation and Analysis of Layout Dependent Effects in Sub-40nm Multi-Ring and Multi-Finger nMOSFETs for High Frequency Applications
    (2019-01-01)
    Li, Zu-Cheng
    ;
    Guo, Jyh-Chyurn
    ;
    Lin, Jinq-Min
    ;
    交大名義發表
    ;
    National Chiao Tung University
    Multi-finger (MF) and multi-ring (MR) nMOSFETs were designed and fabricated in 40nm CMOS technology to explore the layout dependent effects in key device parameters and parasitic RC responsible for RF performance. For the first time, the experimental proves the advantages of MR nMOSFETs, such as the increase of effective mobility (mu(eff)), transconductance (g(m)), and channel current (I-DS), and smaller parasitic source resistance (R-S), all of which are in favor of higher speed and higher frequency. However, the undesired increase of 3-D fringing capacitances may bring a critical trade-off influencing high frequency performance. In this paper, new observation and in-depth analysis of the complicated layout dependent effects can facilitate the device layout optimization in the right direction for RF and mm-wave design and applications.
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    The Impact of Layout Dependent Intrinsic Parasitic RLC on High Frequency Performance in 3T and 4T Multi-finger nMOSFETs
    (2019-01-01)
    Guo, Jyh-Chyurn
    ;
    Ou, Jyun-Rong
    ;
    Lin, Jinq-Min
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A new observation of significant differences in the high frequency device parameters and performance like f(T) and f(MAX) is identified from the comparison of 3-terminal (3T) and 4-terminal (4T) multi-finger (MF) nMOSFETs. Through an extensive characterization on the intrinsic Z- and Y-parameters, it is found that the major impact comes from the particular increase of intrinsic parasitic resistances and inductances at the source terminal, namely R-s,R-int and L-s,L-int in the 4T MF MOSFETs. The proposed analytical models as a function of key device parameters incorporating the influence of the intrinsic parasitic RLC through high frequencies can accurately predict f(T) and f(MAX) degradation in 4T MF nMOSFETs as well as the complicated layout dependent effects. The experimental results and analytical models can be useful to facilitate MF devices layout optimization for high frequency design and performance improvement.
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    Low Power UWB CMOS LNA Using Resistive Feedback and Current-Reused Techniques Under Forward Body Bias
    (2017-01-01)
    Guo, Jyh-Chyurn
    ;
    Lin, Ching-Shiang
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A ultra-wideband (UWB) low noise amplifier (LNA) has been realized in 0.18 mu m CMOS technology. The current-reused method combined with forward body bias (FBB) in a cascade amplifier can enable an aggressive voltages scaling, such as V-DD and V-G1 to 1.0V and 0.53V, i.e. 44.5% and 70.6% reduction compared to the typical VDD of 1.8V. The low voltage feature from FBB leads to more than 50% saving of power dissipation to 5.2mW. The on-chip measurement indicates power gain (S-21) of 10.55 similar to 12.6dB and noise figure (NF50) of 3.2 similar to 3.95 dB through the UWB (3 similar to 10.5GHz). This UWB LNA with small chip area (0.69mm(2)) provides a solution for low voltages, low power, and low cost.
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    Low Voltage and Low power UWB CMOS LNA using Current-Reused and Forward Body Biasing Techniques
    (2017-01-01)
    Guo, Jyh-Chyurn
    ;
    Lin, Ching-Shiang
    ;
    Liang, Yu-Tang
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A ultra-wideband (UWB) low noise amplifier (LNA) was designed and fabricated in 0.18 mu m CMOS technology. The successful integration of current-reused and forward body biasing (FBB) techniques in a cascade amplifier can enable an aggressive scaling of the supply voltages, V-DD and V-G1 to 1.0V and 0.53V. The low voltage feature from FBB leads to more than 50% saving of power dissipation to 5.2mW. The measured power gain (S-21) can reach 10.55 similar to 12.6dB and noise figure (NF50) is 3.2 similar to 3.95 dB through the UWB (3 similar to 10.5GHz). This UWB LNA with small chip area (0.69mm(2)) provides a solution of low voltages, low power, and low cost.
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    The Impact of Uniaxial Strain on Flicker Noise and Random Telegraph Noise of SiC Strained nMOSFETs in 40nm CMOS Technology
    (2011-01-01)
    Yeh, Kuo-Liang
    ;
    Chang, Chih-Shiang
    ;
    Guo, Jyh-Chyurn
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The impact of uniaxial strain on flicker noise and random telegraph noise (RTN) was investigated in frequency and time domains, respectively. Both control and SiC strained nMOS reveal flicker noise dominated by number fluctuation model but the latter one with uniaxial strain suffers significantly higher noise. RTN measured from SiC strained nMOS features a complex spectrum with multi-level drain current fluctuation amplitudes. The capture time (tau(c)), emission time (tau(e)), and effective trap depth (Z(eff)) can be extracted to explore the impact from the uniaxial strain on trap properties, RTN, and flicker noise.
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    A Comprehensive Characterization Method for Lateral Profiling of Interface Traps and Trapped Charges in P-SONOS Cell Devices
    (2017-03)
    Guo, Jyh-Chyurn
    ;
    Du, Pei-Ying
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A comprehensive characterization method has been developed in this paper for reliable lateral profiling of the interface traps (Delta N-it), localized charges (Delta N-ot), and trapped holes (Delta N-hole) in P-SONOS cell devices. Charge pumping current (I-CP) measurement can be used to probe Delta N-it and Delta N-ot from the increase of maximum I-CP (I-CP,I- max) and the shift of I-CP curve along the base level voltage (V-b). When increasing the program and erase (P/E) cycles, the negative threshold voltage (V-T) shift at both program and erase states suggests the generation of Delta N-hole. The evolution of Delta N-it, Delta N-ot, and Delta N-hole during P/E cycling can consistently explain the nonmonotonic variations of gate induced drain leakage current (I-GIDL) and substrate current (I-SUB) as well as dramatic differences between the source and drain. The lateral migration of Delta N-ot caused by extending P/E cycles may lead to the failure of two-bit operation in SONOS cell devices. The larger V-T shift and subthreshold swing, smaller read current, and lower transconductance may degrade the endurance and retention of P-SONOS when applied in Flash memory.
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    The Impact of Layout Dependent Effects on Mobility and Flicker Noise in Nanoscale Multifinger nMOSFETs for RF and Analog Design
    (2016)
    Guo, Jyh-Chyurn
    ;
    Lo, Yi-Zen
    ;
    Ou, Jyun-Rong
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The impact of layout dependent effects on multi-finger (MF) device parameters, such as transconductance (g(m)), effective mobility (mu(eff)), source resistance (R-S), and flicker noise was investigated in this paper to facilitate RF and analog optimization design. MF devices with wide poly-to-poly (PO-PO) space can achieve higher mu(eff) and two-end source line layout can effectively reduce R-S to improve g(m). However, the wide PO-PO space yielding higher mu(eff) cannot ensure lower flicker noise in nMOSFETs, which is dominated by number fluctuation model.
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    The Impact of Layout Dependent Stress and Gate Resistance on High Frequency Performance and Noise in Multifinger and Donut MOSFETs
    (2013)
    Ku, Chih-You
    ;
    Yeh, Kuo-Ling
    ;
    Guo, Jyh-Chyurn
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The impact of STI stress on mobility and resulted transconductance (g(m)) degradation appear as a penalty of multi-finger devices for RF and analog design. Donut device layout is proposed to eliminate the STI transverse stress and achieve higher g(m). Both NMOS and PMOS can benefit from the donut layout, with higher cut-off frequency (f(T)). However, the layout dependence of g(m) and gate resistance (R-g) becomes a critical trade-off in determining high frequency performance other than f(T), such as maximum oscillation frequency (f(max)) and RF noise. In this paper, a comparison between multi-finger and donut MOSFETs in terms of f(T), f(max), and NFmin can provide a useful guideline of device layout for RF design using nanoscale CMOS technology.