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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Kao, Kuo-Hsing

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Now showing 1 - 10 of 22
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    Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters
    (2020-09-01)
    Sung, Po-Jung
    ;
    Chang, Shu-Wei
    ;
    Kao, Kuo-Hsing
    ;
    Wu, Chien-Ting
    ;
    Su, Chun-Jung
    In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness (T-Si) was obtained by dry etching and wet etching processes. The channel thickness is controlled by dry etching, and the channel width was shrunk down by wet etching. Compared to single nanowire field-effect transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For the CMOS inverter, the voltage transfer characteristics (VTCs) could be matched much better by adjusting the channel widths and layers for N-channel MOSFET (NFET) and P-channel MOSFET (PFET), respectively. For the CFET inverter, layout areas could be reduced and requires less number of lithographic and ion implantation steps contrary to the CMOS inverter. However, we observe that the VTCs of the CFET inverters still show asymmetric behavior due to the difficulties of adjustment in NS layers and systematic behavior of threshold voltages for NFETs/PFETs. This work experimentally demonstrates the CMOS and CFET inverters on the vertically stacked NS structure, which is promising for system-on-panel (SoP) and 3-D-ICs applications.
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    Impact of the polarization on time-dependent dielectric breakdown in ferroelectric Hf0.5Zr0.5O2 on Ge substrates
    (2020-04-01)
    Yang, Ting-Hsin
    ;
    Su, Chun-Jung
    ;
    Wang, Yu-Shun
    ;
    Kao, Kuo-Hsing
    ;
    Lee, Yao-Jen
    In this work, polarization-dependent time-dependent dielectric breakdown in ferroelectric HZO Ge MOSCAPs presented. First, ferroelectric HZO Ge MOSCAPs with and without in-situ NH3 plasma interfacial layer, treatment exhibit the two distinct remnant polarization (P-r), Secondly the device with a larger P-r shows a higher gate leakage current and smaller time-to-breakdown (t(BD)) compared to the device with a smaller P-r. Then, a physical model based on the high probability of the electron tunneling accelerating the formation of the percolation path is proposed. Finally, the device with large P-r shows a lower extrapolated operating voltage. However more than 1.5 V of the extracted operation voltage for 1% failure of 10 year lifetime in the device with large P-r still can be obtained. (C) 2020 The Japan Society of Applied Physics
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    Demonstration of Annealing-free Metal-Insulator-Semiconductor (MIS) Ohmic Contacts on a GaN Substrate using Low Work-function Metal Ytterbium (Yb) and Al2O3 Interfacial Layer
    (2019-01-01)
    Wu, Tian-Li
    ;
    Tseng, Yang-Yan
    ;
    Huang, Chih-Fang
    ;
    Chen, Zih-Sin
    ;
    Lin, Chih-Chien
    In this letter, the Metal-Insulator-Semiconductor (MIS) contacts are fabricated on the GaN substrates and compared to the Metal-Semiconductor (MS) contacts. To alleviate the Fermi level pinning effect at the Metal-Semiconductor interface, an Al2O3 interfacial layer (IL) (1 similar to 3 nm) is used to form the MIS contacts. By comparing the electrical characteristics, the contact with Onm Al2O3 layer, i.e., MS contact, shows a lowest current compared to the contacts with an Al2O3 IL, i.e., MIS contact. Furthermore, the current at 0.5V in the fabricated Transmission Line Measurement (TLM) device with lnm Al2O3 IL is 10(3) times higher the one without an Al2O3 IL. This proves that inserting an Al2O3 IL could mitigate the Fermi level pinning, resulting in a low Schottky barrier height. Finally, based on the TLM analysis, the resistivity of 5.1x10(-4) Omega.cm(2) is demonstrated in the MIS contact with lnm Al2O3 IL.
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    X-ray photoelectron spectroscopy energy band alignment of spin-on CoTiO3 high-k dielectric prepared by sol-gel spin coating method
    (2008-09-01)
    Kao, Kuo-Hsing
    ;
    Chuang, Shiow-Huey
    ;
    Wu, Woei-Cherng
    ;
    Chao, Tien-Sheng
    ;
    Chen, Jian-Hao
    The characteristics of CoTiO3 high-k dielectric prepared by sol-gel spin coating method had been demonstrated. High electrical permittivity (k similar to 40.2) of CoTiO3 dielectric was extracted via the transmission electron microscopy image and capacitance-voltage curves. In addition, the valence band offset between thermal SiO2 and spin-on CoTiO3 was about 4.0 eV, which was detected by x-ray photoelectron spectroscopy. The band gaps of thermal SiO2 and spin-on CoTiO3 were 9.0 and 2.2 eV, respectively. Energy band alignment of spin-on CoTiO3 directly with SiO2 and indirectly with Si was determined in this work. (c) 2008 American Institute of Physics.
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    Junctionless FETs With a Fin Body for Multi-V-TH and Dynamic Threshold Operation
    (2018-08-01)
    Kumar, Malkundi Puttaveerappa Vijay
    ;
    Lin, Jer-Yi
    ;
    Kao, Kuo-Hsing
    ;
    Chao, Tien-Sheng
    ;
    電子物理學系
    In this paper, a n-type junctionless FET (JLFET) with a p-type fin body (FB) is investigated using a 3-D numerical simulator. We show that the proposed device (FB-JLFET) with a p+FB can control the electrostatic potential of the channel more efficiently for multi-V-TH (threshold voltage) and dynamic threshold (DT) operation. Moreover, body bias application is implemented in FB-JLFET and a large body factor (gamma) is predicted for wide range V-TH modulation. Thanks to the stronger potential coupling between the channel and FB, the proposeddevice exhibits gamma improvement compared to the conventional JL bulk FinFETs under the same electrostatic control. In addition, DT operation is studied in the form of a JLFET for the first time and it exhibits 37% improvement of the on-state drive current and better subthreshold swing (S.S.) compared to FB-JLFET without DT. This paper provides the feasibility of multi-V-TH operation with body bias mode for high performance or low-power applications and DT operation for high-speed circuits with low power consumption.
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    Ultra-Shallow Junction Formation by Monolayer Doping Process in Single Crystalline Si and Ge for Future CMOS Devices
    (2017-01-01)
    Chuang, Shang-Shiun
    ;
    Cho, Ta-Chun
    ;
    Sung, Po-Jung
    ;
    Kao, Kuo-Hsing
    ;
    Chen, Henry J. H.
    We focused on the damage-free monolayer doping (MLD) method starting from a chemical reaction of molecules on Si and Ge surfaces and applied it to 3D MOSFET device fabrication. MLD methods were verified by different material analysis, such as XPS and Raman spectroscopy. For a Si-based FinFET structure, compared to the device with ion implantation, the short channel effect of source and drain (SD) extension regions formed by MLD are improved. The shallower SD extension regions formed by low-temperature microwave annealing (MWA) are expected to the device showing better electrical properties than deeper ones formed by RTA. In addition, formation of the n- and p-type doping in Ge by MLD was also investigated. Even after annealing at 800 degrees C for 300 sec by RTA, the p-type doping still exhibits a low surface doping concentration due to the low diffusion coefficient of B in Ge and surface diffusion limitations at the MLD/Ge interface. By using a combination of RTA and CO2 laser spike annealing (LSA), MLD n-type doping in Ge are formed with junction depths of approximate to 15 nm, and peak concentration of approximate to 6 x 10(20) atoms/cm(3). The dopant activation for the MLD-doped channels of Ge junctionless FinFETs (JLFinFETs) is improved after the additional CO2 LSA. (C) 2017 The Electrochemical Society. All rights reserved.
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    Improving the Electrical Performance of a Quantum Well FET With a Shell Doping Profile by Heterojunction Optimization
    (2017-09-01)
    Kumar, Malkundi Puttaveerappa Vijay
    ;
    Hu, Chia-Ying
    ;
    Walke, Amey Mahadev
    ;
    Kao, Kuo-Hsing
    ;
    Chao, Tien-Sheng
    This paper investigates the impacts of typical semiconductor material properties-electron affinity, bandgap, and dielectric constant, on the electrical performance of a p-type core-shell heterojunction nanowire FET by numerical simulations. At the heterojunction, a valence band offset of 200 meV forms a sufficient energy barrier confining the holes in the quantum well, resulting in the optimal OFF-state current. A higher dielectric constant of the shell region is found to be able to decrease the leakage current of the device. The optimum conditions from the parameter analysis are demonstrated by a realistic and achievable material combination of Si/SiGe for the core-shell configuration. This paper provides physical insights into the materialwise impacts for designing the proposed transistor showing the reduced OFF-current and a better subthreshold swing for low-power applications.
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    Fluorinated HfO2 Gate Dielectrics Engineering for CMOS by pre- and post-CF4 Plasma Passivation
    (2008)
    Wu, Woei-Chemg
    ;
    Lai, Chao-Sung
    ;
    Lee, Shih-Ching
    ;
    Ma, Ming-Wen
    ;
    Chao, Tien-Sheng
    In this paper, we demonstrate TaN/Fluorinated HfO2 CMOS devices, focusing on symmetry and asymmetry fluorine incorporation at top or bottom HfO2 interfaces. 16% permittivity enhancement, 65% and 91% mobility increases for electron and hole, respectively, under high electric field was achieved. Reliability of n- and p-MOSFET was improved 3 orders and 8% for GIDL and hot carrier immunity, respectively. A physical model of shallow and deep trapping level affected by fluorine was proposed to explain the NBTI and PBTI improvements.
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    High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications
    (2015)
    Lee, Yao-Jen
    ;
    Cho, Ta-Chun
    ;
    Sung, Po-Jung
    ;
    Kao, Kuo-Hsing
    ;
    Hsueh, Fu-Kuo
    A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth (< 5nm) and an abrupt steepness (< 0.8 nm/dec). The dopant activation of the devices experienced MLD and MWA is further enhanced by the nonmelting COLSA without dopant diffusion, and which can also avoid fin deformation and recover surface defects left by fin patterning. Thanks to the enhanced dopant activation by COLSA, the SDP-FinTFTs overall exhibit better performance than the SDP-FinTFTs without COLSA and the conventional implanted (imp) FinTFTs in terms of subthreshold swing (S.S.), on-currents (I-on by 160% compared to the SDP-FinTFTs without COLSA) and on/off current ratio (I-on/I-off > 10(7)) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.
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    Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technology
    (2015)
    Lee, Yao-Jen
    ;
    Hou, Fu-Ju
    ;
    Chuang, Shang-Shiun
    ;
    Hsueh, Fu-Kuo
    ;
    Kao, Kuo-Hsing
    We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge0.9Si0.1 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl-2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an I-on/I-off ratio exceeding 10(8), the highest ever reported for Ge-based pFETs.