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Has files: NoSubject: search.filters.subject.electrostatic discharge (ESD)

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Now showing 1 - 10 of 17
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    RF/High-Speed I/O ESD Protection: Co-optimizing Strategy Between BEOL Capacitance and HBM Immunity in Advanced CMOS Process
    (2020-07-01)
    Wu, Wei-Min
    ;
    Ker, Ming-Dou
    ;
    Chen, Shih-Hung
    ;
    Chen, Jie-Ting
    ;
    Linten, Dimitri
    In order to meet the requirement of ultrahigh-speed, low latency, and wide bandwidth (BW) in the next 5G mobile network and internet of things (IoT) applications, the parasitic capacitance specification of electrostatic discharge (ESD) protection devices should become much stricter. Reducing the capacitance always degrades the ESD performance in terms of shrinking the size of the ESD protection device. The distributed ESD protection network is one of the solutions which mitigates the capacitance issue and provides a broadband design. However, while the ESD devices are put under the I/O pad in the distributed ESD protection network, back-end-of-line (BEOL) capacitance starts to play an important role in the advanced 28-nm CMOS process. Therefore, a tapered metal structure is proposed to significantly reduce 30% BEOL capacitance of the ESD device, which can gain a 2.8-GHz increase in the operational BW in the distributed network. Meanwhile, it can enhance the human-body-model (HBM) level up to 16% higher than the original layout style under the same front-end-of-line (FEOL) layout size.
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    Design of Fin-Diode-Triggered Rotated Silicon-Controlled Rectifier for High-Speed Digital Application in 16-nm FinFET Process
    (2020-07-01)
    Chang, Rong-Kun
    ;
    Lin, Chun-Yu
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The FinFET architecture has widely been used in the digital circuit application, due to the good short channel effect control and driving current boost. However, the worse thermal dispassion and smaller effective silicon volume would cause the significant impacts during the circuits under electrostatic discharge (ESD) event. Thus, the ESD protection device should be installed into the high-speed digital circuit to enhance the ESD robustness. To avoid the effect of circuit performance, the parasitic capacitance of ESD device must be as low as possible. In this article, two types of Fin-diode-triggered rotated silicon-controlled rectifier (SCR) with dual ESD current path have been proposed and verified in a 16-nm FinFET CMOS process. The proposed devices have better current-handling capability, sufficiently low parasitic, compact layout area, and low leakage current.
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    On-chip Transient Detection Circuit for Microelectronic Systems against Electrical Transient Disturbances due to ESD Events
    (2018-01-01)
    Chen, Wen-Chieh
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A new on-chip transient detection circuit which can detect electrical disturbances of system-level electrostatic discharge (ESD) is proposed. The circuit is designed with reduced physical area by utilizing dual-latched structure. With hardware/firmware co-design method, auto-recovery procedure can be activated by the detection circuit when microelectronic systems suffer system-level ESD events. The immunity level of microelectronic products against the electromagnetic interference (EMI) of ESD events can be effectively improved. The proposed on-chip transient detection circuit has been verified in a 0.18-mu m CMOS process with 1.8-V devices under system-level ESD tests.
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    ESD Protection Design with Low-Leakage Consideration for Silicon Chips of IoT Applications
    (2017-01-01)
    Ker, Ming-Don
    ;
    Lin, Chun-Yu
    ;
    Wu, Yi-Han
    ;
    Wang, Wen-Tai
    ;
    電子工程學系及電子研究所
    On-chip electrostatic discharge (ESD) protection design with low-leakage consideration for the silicon chips of IoT applications is presented. The proposed ESD protection design uses the fast turn-on silicon-controlled rectifier (SCR) device to implement the power-rail ESD clamp circuit. Experimental results verified in TSMC 28nm CMOS process have shown that the proposed design has advantages of low leakage current (2 similar to 3nA), low trigger voltage (similar to 2V), high ESD robustness (>8kV), and free to latchup issue.
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    Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
    (2010-11-01)
    Yeh, Chih-Ting
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The RC-based power-rail ESD clamp circuit with the n-channel metal-oxide-semiconductor (NMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based ESD-transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions.
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    New On-Chip Transient Detection Circuit to Improve Electromagnetic Susceptibility of Microelectronic Systems
    (2017-01-01)
    Kang, Xiao-Rui
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is presented in this work. The circuit simulation and experimental results with silicon testchip in a 0.18-mu m CMOS process have continued that the new proposed circuit can successfully detect the occurrence of system-level ESD-induced electrical transient disturbance. The detection output can be used as system recovery index to restore the system from frozen or upset state to a stable and known state. Therefore, the immunity of microelectronic products against the system-level ESD test can be effectively enhanced.
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    Self-Reset Transient Detection Circuit for On-Chip Protection Against System-Level Electrical-Transient Disturbance
    (2018-03-01)
    Kang, Xiao-Rui
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A new self-reset transient detection circuit for on-chip protection against a system-level electrical-transient disturbance is proposed. This circuit is designed to detect the occurrence of system-level electrical-transient disturbance events, and automatically reset the system to initial state for the next detection. In addition, the reset time can be adjusted to meet the different requests of system recovery time in microelectronic products. The circuit performance has been investigated by HSPICE simulation and verified in silicon chip. The experiment results in a 0.18-mu m complementary metal-oxide semiconductor (CMOS) process with 1.8-V devices have confirmed the detection and self-reset functions of the proposed on-chip self-reset transient detection circuit under system-level electrostatic discharge and electrical-fast-transient testing conditions. With firmware co-design, the proposed detection circuit can provide an effective on-chip solution to recover the microelectronic system from the system-level transient disturbance-induced abnormal state to a known stable state. Therefore, the immunity level of microelectronic products equipped with CMOS integrated circuits against electromagnetic susceptibility can be effectively enhanced.
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    Design of Power-Rail ESD Clamp With Dynamic Timing-Voltage Detection Against False Trigger During Fast Power-ON Events
    (2018-03-01)
    Chen, Jie-Ting
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The RC-based power-rail electrostatic discharge (ESD) clamp with nMOS of large size has been widely utilized to enhance the ESD robustness of CMOS integrated circuits. However, such circuit design that only detects the rising time of ESD pulse may be accidentally triggered in some conditions, such as fast power-ON, hot-plug, and envelope tracking applications. In this paper, a new power-rail ESD clamp circuit with transient and voltage detection function has been proposed and implemented in a 0.18-mu m 1.8-V CMOS technology. The measurement results from the silicon chip have demonstrated that the new proposed power-rail ESD clamp circuit with adjustable minimum starting voltage (V-starting) can achieve good ESD robustness and avoid triggering under fast power-ON condition. In addition, the proposed circuit has a low standby leakage current of 270 nA at 125 degrees C under normal power-ON condition.
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    On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology
    (2017-10-01)
    Chen, Jie-Ting
    ;
    Lin, Chun-Yu
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly requested in high-speed I/O applications. The traditional methods to reduce parasitic capacitance were using a stacked diode or a stacked diode with embedded silicon-controlled rectifier (SCR). The stacked diode or the stacked diode with embedded SCR would have larger turn-on resistance to cause a higher clamping voltage. It should be further improved to achieve good ESD protection effectiveness for the high-speed I/O applications. In this paper, a new ESD protection device with reduced parasitic capacitance and smaller turn-on resistance to improve ESD protection effectiveness is proposed. The measurement results from the silicon chip have demonstrated that the proposed ESD device can achieve smaller parasitic capacitance, lower turn-on resistance, and higher ESD robustness, compared with the conventional devices. The proposed ESD protection device is very suitable to protect the high-speed I/O circuits in nanoscale CMOS technology.
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    Study on the ESD-Induced Gate-Oxide Breakdown and the Protection Solution in 28nm High-K Metal-Gate CMOS Technology
    (2015)
    Lin, Chun-Yu
    ;
    Ker, Ming-Dou
    ;
    Chang, Pin-Hsin
    ;
    Wang, Wen-Tai
    ;
    電子工程學系及電子研究所
    To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.