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Subject: search.filters.subject.TiLaO

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Now showing 1 - 5 of 5
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    High Performance of Ge nMOSFETs Using SiO2 Interfacial Layer and TiLaO Gate Dielectric
    (2010-01-01)
    Chen, W. B.
    ;
    Chin, Albert
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Using a SiO2 interfacial layer and a high-kappa gate TiLaO dielectric, the TaN/TiLaO/SiO2 on Ge/Si nMOSFETs in this study showed a small 1.1-nm capacitance equivalent thickness, a good high field mobility of 201 cm(2)/(V . s) at 0.5 MV/cm, and a very low OFF-state leakage current of 3.5 x 10(-10) A/mu m. The self-aligned and gate-first metal-gate/high-kappa and Ge nMOSFETs were processed using standard ion implantation and 550 degrees C RTA. The proposed devices are fully compatible with current VLSI fabrication methods.
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    TiO2-Based Indium Phosphide Metal-Oxide-Semiconductor Capacitor with High Capacitance Density
    (2015-04-01)
    Cheng, Chun-Hu
    ;
    Hsu, Hsiao-Hsuan
    ;
    Chou, Kun-I
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    We report a low-temperature InP p-MOS with a high capacitance density of 2.7 mu F/cm(2), low leakage current of 0.77 A/cm(2) at 1 V and tight current distribution. The high-density and low-leakage InP MOS was achieved by using high-kappa TiLaO dielectric and ultra-thin SiO2 buffer layer with a thickness of less than 0.5 nm. The obtained EOT can be aggressively scaled down to <1 nm through the use of stacked TiLaO/SiO2 dielectric, which has the potential for the future application of high mobility III-V CMOS devices.
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    Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack
    (2013-09-01)
    Cheng, C. H.
    ;
    Chou, K. I.
    ;
    Chin, A.
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    We report a self-aligned and gate-first TiLaO/La2O3 n-MOSFET with an equivalent oxide thickness (EOT) of 0.57 nm and low threshold voltage (V-t) of 0.3 V. The small EOT MOSFET can be reached using La-based interfacial layer with strong bond enthalpy (La-O, 799 kJ/mol) to suppress the formation of defect-rich low- interfacial layer and simultaneously block titanium atom inter-diffusion to avoid additional EOT increase. This gate-first low-EOT MOSFET exhibits the potential to integrate with current CMOS process. (C) 2013 Elsevier B.V. All rights reserved.
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    Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO2 gate stack
    (2013-04-01)
    Cheng, C. H.
    ;
    Chou, K. I.
    ;
    Chin, Albert
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (V-t) of 0.31 V. This small EOT MOSFET was achieved by employing high-kappa CeO2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-kappa SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node. (C) 2013 Elsevier Ltd. All rights reserved.
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    Improved high-temperature leakage in high-density MIM capacitors by using a TiLaO dielectric and an Ir electrode
    (2007-12-01)
    Cheng, C. H.
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    Pan, H. C.
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    Yang, H. J.
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    Hsiao, C. N.
    ;
    Chou, C. P.
    We have fabricated high-kappa. TaN/Ir/TiLaO/TaN metal-insulator-metal capacitors. A low leakage current of 6.6 x 10(-7) A/cm(2) was obtained at 125 degrees C for 24-fF/mu m(2) density capacitors. The excellent device performance is due to the combined effects of the high-kappa TiLaO dielectric, a high work-function Ir electrode, and large conduction band offset.