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Subject: search.filters.subject.floating-body effect

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Now showing 1 - 7 of 7
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    Low-frequency noise in partially depleted SOI MOSFETs operating from linear region to saturation region at various temperatures
    (2004-04-01)
    Chen, KM
    ;
    Hu, HH
    ;
    Huang, GW
    ;
    Yeh, WK
    ;
    Chang, CY
    The low-frequency noise characteristics of partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) in silicon-on-insulator technology at various temperatures were investigated. For floating-body devices, a Lorentzian-like noise overshoot is observed due to the floating-body effect. The noise overshoot is dependent on temperature and bias, and can be reduced using a source-to-body-connected structure. At high temperature or high drain bias, the 1/f noise will be observed, and it is temperature-independent due to the trap-induced mobility fluctuation in the channel.
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    Suppression of the floating-body effect in poly-Si thin-film transistors with self-aligned Schottky barrier source and ohmic body contact structure
    (2004-09-01)
    Kuo, PY
    ;
    Chao, TS
    ;
    Lei, TF
    ;
    電子工程學系及電子研究所
    ;
    奈米中心
    In this letter, we developed a new self-aligned Schottky barrier source and ohmic body contact (SSOB) method that can effectively suppress the floating-body effect in poly-Si thin-film transistors (TFTs). Experimental results,show that the SSOB-TFTs give higher output resistance, less threshold voltage variation, improved subthreshold characteristics, and larger breakdown voltage compared with conventional TFTs. The characteristics of the SSOB-TFTs are suitable for high-performance driving TFTs with a high output resistance and large breakdown voltage.
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    Modeling geometry-dependent floating-body effect using body-source built-in potential lowering for SOI circuit simulation
    (2005-04-01)
    Su, P
    ;
    Lee, W
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper presents a compact silicon-on-insulator (SOI) model to capture the geometry-dependent floating-body effect using the body-source built-in potential lowering approach. This physically accurate model circumvents the modeling challenge imposed by the trend of the coexistence of partial-depletion (PD) and full-depletion (FD) devices in a single SOI chip by considering short-channel, reverse short-channel and reverse narrow-width floating-body effects. The implication on circuit simulation, under the unified Berkeley short-channel IGFET model-silicon-on-insulator (BSIMSOI) framework, has also been addressed. This geometry-dependent body-source built-in potential lowering model will further enhance the device design of scaled SOI complementary metal-oxide-semiconductor (CMOS) below 100 nm.
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    Degradation of low-frequency noise in partially depleted silicon-on-insulator metal oxide semiconductor field-effect transistors by hot-carrier stress
    (2005-06-01)
    Chen, KM
    ;
    Hu, HH
    ;
    Huang, GW
    ;
    Chang, CY
    ;
    電子工程學系及電子研究所
    In this study, we determined the effects of hot-carrier stress on the low-frequency noise characteristics of partially depleted metal-oxide-semi conductor field-effect transistors (MOSFETs) in silicon-on-insulator (SOI) technology. In devices with a floating-body configuration, kink-related excess noise was observed due to the floating-body effect. The level of this excess noise decreased after normal-mode stress, while it was masked by 1/f noise after reverse-mode stress. The effects of stress-generated interface traps on the drain-to-body leakage current and the floating-body effect were also determined and used to explain the noise behavior. Moreover, the stress-induced 1/f noise degradation in floating-body devices and body-contact devices was studied. It was found that the 1/f degradation of body-contact devices is more significant than that of floating-body devices after hot-carrier stress.
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    On the prediction of geometry-dependent floating-body effect in SOI MOSFETs
    (2005-07-01)
    Su, P
    ;
    Lee, W
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This brief demonstrates that, through the perspective of body-source built-in potential lowering (Delta V-bi), the geometry-dependent floating-body effect in state-of-the-art silicon-on-insulator (SOI) MOS-FETs can be explained and predicted by the geometry dependence of threshold voltage (V-T). The correlation between Delta V-bi and V-T unveiled in this brief is the underlying mechanism responsible for the coexistence of partially depleted and fully depleted devices in a single SOI chip.
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    High-performance poly-Si TFTs with fully Ni-self-aligned silicided S/D and gate structure
    (2006-04-01)
    Kuo, PY
    ;
    Chao, TS
    ;
    Wang, RJ
    ;
    Lei, TF
    ;
    電子工程學系及電子研究所
    In this letter, fully Ni self-aligned silicided (fully Ni-salicided) source/drain (S/D) and gate polycrystalline silicon thin-film transistors (FSA-TFTs) have been successfully fabricated on a 40-nm-thick channel layer. Experimental results show that the FSA-TFTs give increased ON/OFF current ratio, improved subthreshold characteristics, less threshold voltage rolloff, and larger field-effect mobility compared with conventional TFTs. The FSA-TFTs exhibit small S/D and gate parasitic resistance and effectively suppress the floating-body effect and parasitic bipolar junction transistor action. The characteristics of the FSA-TFTs are suitable for high-performance driving TFTs with good output characteristics and large breakdown voltage.
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    The impact of deep Ni salicidation and NH3 plasma treatment on nano-SOI FinFETs
    (2006-10-01)
    You, Hsin-Chiang
    ;
    Kuo, Po-Yi
    ;
    Ko, Fu-Hsiang
    ;
    Chao, Tien-Sheng
    ;
    Lei, Tan-Fu
    In this letter, 50-nm gate-length nano-silicon-on-insulator FinFETs with deep Ni salicidation and NH3 plasma treatment are fabricated. It is found that device performances, including subthreshold slope (SS) drain-induced barrier lowering (DIBL) and OFF-state leakage current, can be greatly improved by using deep Ni salicidation process compared to no Ni salicidation process. The deep Ni-salicided devices effectively suppress the floating-body effect and parasitic bipolar junction. transistor action. In addition, the effect of NH3 plasma on the deep Ni-salicided devices is discussed. Experimental results reveal that the devices under a new state-of-the-art NH3 plasma process can achieve better performance such as an SS of 66 mV/dec and a DIBL of 0.03 V.