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Low-Frequency Noise Characterization of AlGaN & x002F;GaN HEMTs and MIS-HEMTs Under UV Illumination
(2020-01-01)
Nagarajan, Venkatesan
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Chen, Kun-Ming
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Lin, Hsin-Yi
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Hu, Hsin-Hui
;
Huang, Guo-Wei
The low-frequency noise characteristics of AlGaN & x002F;GaN HEMTs and MIS-HEMTs are investigated in the dark condition and under UV illumination. The test devices with a 3-& x03BC;m-thick GaN buffer and a 25-nm-thick Al_0.22Ga_0.78N barrier layer were fabricated on the silicon wafer. For MIS-HEMTs, a 25-nm-thick SiN layer was deposited as a gate dielectric. The measured low-frequency noises show a 1 & x002F;f spectrum and can be described by the carrier number fluctuation model. Different noise responses to the UV light between HEMTs and MIS-HEMTs were observed. By comparing the noise data in dark and under UV illumination, the noise sources under the gate and in the ungated gate-drain access region have been identified. From these results, we can find a design guideline to improve the noise and reliability of GaN-based devices for optoelectronic applications.
A Triode Device with a Gate Controllable Schottky Barrier: Germanium Nanowire Transistors and Their Applications
(1970-01-01)
Lin, Che-Yi
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Chen, Chao-Fu
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Chang, Yuan-Ming
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Yang, Shih-Hsien
;
Lee, Ko-Chun
Electrical contacts often dominate charge transport properties at the nanoscale because of considerable differences in nanoelectronic device interfaces arising from unique geometric and electrostatic features. Transistors with a tunable Schottky barrier between the metal and semiconductor interface might simplify circuit design. Here, germanium nanowire (Ge NW) transistors with Cu3Ge as source/drain contacts formed by both buffered oxide etching treatments and rapid thermal annealing are reported. The transistors based on this Cu3Ge/Ge/Cu3Ge heterostructure show ambipolar transistor behavior with a large on/off current ratio of more than 10(5) and 10(3) for the hole and electron regimes at room temperature, respectively. Investigations of temperature-dependent transport properties and low-frequency current fluctuations reveal that the tunable effective Schottky barriers of the Ge NW transistors accounted for the ambipolar behaviors. It is further shown that this ambipolarity can be used to realize binary-signal and data-storage functions, which greatly simplify circuit design compared with conventional technologies.
Effect of NH3 Plasma Nitridation on Hot-Carrier Instability and Low-Frequency Noise in Gd-Doped High-kappa Dielectric nMOSFETs
(2011-03-01)
Chen, Yu-Ting
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Chen, Kun-Ming
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Lin, Cheng-Li
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Yeh, Wen-Kuan
;
Huang, Guo-Wei
The effects of post-NH3 plasma nitridation on device's hot-carrier instability and low-frequency noise in the Hf-based high-kappa/metal-gate n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) with gadolinium (Gd) cap layers are investigated. With postnitridation, the direct-current and 1/f noise characteristics can be improved apparently. Moreover, a hot-carrier stressing-induced threshold voltage shift can be also suppressed despite of a similar transconductance degradation when comparing with that in the device without nitridation. With the charge-pumping and low-frequency noise measurements, we find that the bulk-and interfacial-trap densities can be reduced with nitrogen incorporation. The reduction of bulk and interfacial traps can be contributed to the suppression of Gd diffusion into a high-kappa layer. In this paper, appropriate post-NH3 plasma nitridation can improve the device performance and reliability and low-frequency noise for a gate-first high-kappa/metal-gate nMOSFET with a Gd cap layer.
High Mobilities in Layered InSe Transistors with Indium-Encapsulation-Induced Surface Charge Doping
(2018-11-02)
Li, Mengjiao
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Lin, Che-Yi
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Yang, Shih-Hsien
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Chang, Yuan-Ming
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Chang, Jen-Kuei
Tunability and stability in the electrical properties of 2D semiconductors pave the way for their practical applications in logic devices. A robust layered indium selenide (InSe) field-effect transistor (FET) with superior controlled stability is demonstrated by depositing an indium (In) doping layer. The optimized InSe FETs deliver an unprecedented high electron mobility up to 3700 cm(2) V-1 s(-1) at room temperature, which can be retained with 60% after 1 month. Further insight into the evolution of the position of the Fermi level and the microscopic device structure with different In thicknesses demonstrates an enhanced electron-doping behavior at the In/InSe interface. Furthermore, the contact resistance is also improved through the In insertion between InSe and Au electrodes, which coincides with the analysis of the low-frequency noise. The carrier fluctuation is attributed to the dominance of the phonon scattering events, which agrees with the observation of the temperature-dependent mobility. Finally, the flexible functionalities of the logic-circuit applications, for instance, inverter and not-and (NAND)/not-or (NOR) gates, are determined with these surface-doping InSe FETs, which establish a paradigm for 2D-based materials to overcome the bottleneck in the development of electronic devices.
Low-Frequency Noise Performance of Al-Doped ZnO Nanorod Photosensors by a Low-Temperature Hydrothermal Method
(2017-08-01)
Wang, Zi-Hao
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Yu, Hsin-Chieh
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Yang, Chih-Chiang
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Yeh, Hsin-Ting
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Su, Yan-Kuin
In this paper, we developed a simple hydrothermal method to synthesize vertically aligned ZnO:Al nanorods (NRs) to fabricate a UV photodetector (PD) on a seed layer/glass substrate. The photo-to-dark current ratio of the ZnO: Al NR PD was approximately 1.4 x 10(3) under 1-V bias and UV light irradiation (380 nm). The calculated responsivity of the fabricated PD was 181 A . W-1, and the UV-to-visible rejection ratio of the PD at 1-V applied bias was 1.51 x 10(3). In addition, flicker noise dominated the noise of the ZnO: Al NR PD. The noise-equivalent power and normalized detectivity of the ZnO:Al NR PD were 1.17 x 10(-11) W and 4.03 x 10(12) cm . Hz(0.5)W(-1), respectively.
The impact of electrical contacts and contact-induced ultralow noise amplitudes in layered transistors
(2016-12)
Hsu, Chih-Kai
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Lin, Chi-Yi
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Li, Wenwu
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Sun, Huabin
;
Xu, Yong
Electrical contacts made of conducting channels with external circuitry significantly impact electronic performances, in particular for two-dimensional semiconductors. This work presents a systematic study of back-to-back Schottky contacts to a layered compound of semiconducting flakes through static and dynamic electrical measurements and the first demonstration of Schottky barrier-dominated, p-type PbSnS2 field-effect transistors. In the static analysis, the Schottky barrier height of the layered transistors can be modulated by applied electrostatic fields, while the contact-dominated fluctuations render to the 1/f electric noise and induce a normalized noise amplitude in the order of 10(-9)-10(-8). Such an ultralow-noise amplitude, which is never observed in other layered semiconducting transistors, is ascribed to the existence of Schottky barriers. Our experimental results provide a nuanced perspective for advancing the understanding of performance limit with increasing numbers of layers for electronic development.
Low-frequency noise in partially depleted SOI MOSFETs operating from linear region to saturation region at various temperatures
(2004-04-01)
Chen, KM
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Hu, HH
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Huang, GW
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Yeh, WK
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Chang, CY
The low-frequency noise characteristics of partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) in silicon-on-insulator technology at various temperatures were investigated. For floating-body devices, a Lorentzian-like noise overshoot is observed due to the floating-body effect. The noise overshoot is dependent on temperature and bias, and can be reduced using a source-to-body-connected structure. At high temperature or high drain bias, the 1/f noise will be observed, and it is temperature-independent due to the trap-induced mobility fluctuation in the channel.
Degradation of low-frequency noise in partially depleted silicon-on-insulator metal oxide semiconductor field-effect transistors by hot-carrier stress
(2005-06-01)
Chen, KM
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Hu, HH
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Huang, GW
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Chang, CY
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電子工程學系及電子研究所
In this study, we determined the effects of hot-carrier stress on the low-frequency noise characteristics of partially depleted metal-oxide-semi conductor field-effect transistors (MOSFETs) in silicon-on-insulator (SOI) technology. In devices with a floating-body configuration, kink-related excess noise was observed due to the floating-body effect. The level of this excess noise decreased after normal-mode stress, while it was masked by 1/f noise after reverse-mode stress. The effects of stress-generated interface traps on the drain-to-body leakage current and the floating-body effect were also determined and used to explain the noise behavior. Moreover, the stress-induced 1/f noise degradation in floating-body devices and body-contact devices was studied. It was found that the 1/f degradation of body-contact devices is more significant than that of floating-body devices after hot-carrier stress.
Excess low-frequency noise in ultrathin oxide n-MOSFETs arising from valence-band electron tunneling
(2005-09-01)
Wu, JW
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You, JW
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Ma, HC
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Cheng, CC
;
Hsu, CF
Low-frequency flicker noise in analog n-MOSFETs with 15-angstrom gate oxide is investigated. A new noise generation mechanism resulting from valence-band electron tunneling is proposed. In strong inversion conditions, valence-band electron tunneling from Si substrate to polysilicon gate takes place and results in the splitting of electron and hole quasi-Fermi-levels in the channel. The excess low-frequency noise is attributed to electron and hole recombination at interface traps between the two quasi-Fermi-levels. Random telegraph signals due to the capture of channel electrons and holes is characterized in a small area device to support our model.
A Comprehensive Investigation of Analog Performance for Uniaxial Strained PMOSFETs
(2009-02-01)
Kuo, Jack Jyun-Yan
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Chen, William Po-Nien
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Su, Pin
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a comprehensive investigation of the analog performance for uniaxial strained PMOSFETs with sub-100 nm gate length. Through a comparison between co-processed strained and unstrained devices regarding important analog metrics such as transconductance to drain current ratio (g(m)/I(d)), dc gain, linearity, low-frequency noise, and device mismatch, the impact of process-induced uniaxial strain on the analog performance of MOS devices has been assessed and analyzed. Our results indicate that, although the drain current noise spectral density and drain current mismatch of the strained device under low gate voltage overdrive are increased because of the larger gate-bias sensitivity of carrier mobility, the strained device has almost the same low frequency and mismatch performance as the unstrained one at a given g(m)/I(d). This paper may provide insights for analog design using advanced strained devices.

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