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Statistical Prediction of Nanosized-Metal-Grain-Induced Threshold-Voltage Variability for 3D Vertically Stacked Silicon Gate-All-Around Nanowiren-MOSFETs
(1970-01-01)
Sung, Wen-Li
;
Li, Yiming
;
交大名義發表
;
電機工程學系
;
電信工程研究所
In this study, we present a statistically accurate model to predict the threshold-voltage variability (sigma V-th) efficiently for three-dimensional (3D) vertically stacked silicon (Si) gate-all-around (GAA) nanowire (NW)n-MOSFETs with multi-channels. The statistical results indicate that the sigma V(th)decreases exponentially by increasing metal grain number (MGN), which is unitless. Additionally, the magnitude of sigma V(th)was calculated for various MGNs, which joins the normality test with Anderson-Darling test. Therefore, the model with MGN can be implemented by nonlinear regression with a regression coefficient of approximately one. From this model and the perspective of process, more 3D vertically stacked channels can reduce the value and sensitivity of sigma V-th. This study provides useful information from statistics to explain the experiment results for 3D vertically stacked Si GAA NWn-MOSFETs with multi-channels.
Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells
(2016-01-01)
Yu, Chang-Hung
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We evaluate and benchmark the performance of logic circuits and stability/performance of 6T SRAM cells using monolayer and bilayer TMD devices based on ITRS 2028 (5.9nm) technology node. For the performance benchmarking of logic circuits, the tradeoff between electrostatic integrity ( monolayer favored) and carrier mobility (bilayer favored), and the issues regarding the uncertainties in the mobility ratio and source/drain series resistance, the underlap device design, and the off-current spec., etc. are comprehensively addressed. In the evaluation of SRAM cells, the cell immunity to random variations is focused. Besides, the impact of high R-SD of TMD materials on RSNM variability is also investigated. The source/drain underlap design is shown to alleviate the larger variability of bilayer SRAM cells. Finally, with superior electrostatics and immunity to random variations, the monolayer TMD devices are favored for low-power logic and SRAM applications; while the bilayer devices, with higher carrier mobility, are more suitable for high-performance logic and SRAM applications.
Physics of Discrete Impurities under the Framework of Device Simulations for Nanostructure Devices
(2018-12-01)
Sano, Nobuyuki
;
Yoshida, Katsuhisa
;
Yao, Chih-Wei
;
Watanabe, Hiroshi
;
電機工程學系
Localized impurities doped in the semiconductor substrate of nanostructure devices play an essential role in understanding and resolving transport and variability issues in device characteristics. Modeling discrete impurities under the framework of device simulations is, therefore, an urgent need for reliable prediction of device performance via device simulations. In the present paper, we discuss the details of the physics associated with localized impurities in nanostructure devices, which are inherent, yet nontrivial, to any device simulation schemes: The physical interpretation and the role of electrostatic Coulomb potential in device simulations are clarified. We then show that a naive introduction of localized impurities into the Poisson equation leads to a logical inconsistency within the framework of the drift-diffusion simulations. We describe a systematic methodology for how to treat the Coulomb potential consistently with both the Poisson and current-continuity (transport) equations. The methodology is extended to the case of nanostructure devices so that the effects of the interface between different materials are taken into account.
Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity
(2011-09-01)
Hu, Vita Pi-Ho
;
Fan, Ming-Long
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
This paper analyzes stability and variability of ultrathin-body (UTB) SOI subthreshold SRAMs considering line- edge roughness (LER), work function variation (WFV), and temperature sensitivity. The intrinsic advantages of UTB SOI technology versus bulk CMOS technology with regard to the stability and variability of 6T SRAM cells for subthreshold operation are analyzed. Compared with LER, WFV causes comparable threshold voltage variation and much smaller subthreshold swing fluctuation, hence less impact on the UTB SOI subthreshold SRAMs. Even considering LER, the Lg = 40 nm UTB SOI 6T subthreshold SRAM cells still provide sufficient margin (mu RSNM/sigma RSNM > 6 at Vdd = 0.3 similar to 0.4 V) while the bulk subthreshold SRAMs with RDF fail to maintain adequate margin. Increasing temperature will increase the Vread,0 and decrease RSNM because of the degraded subthreshold swing. The RSNM of UTB SOI subthreshold SRAMs showless temperature sensitivity compared with that of bulk subthreshold SRAMs. Due to larger body effect, the back-gating technique is more efficient for the Lg = 40 nm and 25 nm UTB SOI subthreshold SRAMs compared with the bulk counterparts. By using lower threshold voltage devices with dual band-gapwork functions, the Lg = 25 nm UTB SOI subthreshold SRAMs show 31.9% reduction in sigma RSNM and 55% improvement in mu RSNM/sigma RSNM.
Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications
(2012-12-01)
Fan, Ming-Long
;
Hu, Vita Pi-Ho
;
Chen, Yin-Nien
;
Su, Pin
;
Chuang, Ching-Te
This paper investigates the impact of intrinsic random variability on the robustness of sense amplifier (SA) for fin-shaped field-effect transistor (FinFET) subthreshold static random access memory (SRAM) applications. We employ a model-assisted statistical approach to consider both fin line edge roughness (fin LER) and work function variation, which are regarded as the major variation sources in an advanced FinFET device. Our results indicate that fin LER dominates the overall variability of subthreshold SA robustness and sensing margin. In addition, it is observed that the offset voltage (V-OS) of current latch SA calculated solely from threshold voltage (V-T) mismatch underestimates the actual variation and is shown to be optimistic. For large-signal single-ended inverter sensing, we find that sense "0" hinders the allowable sensing margin and needs to be carefully designed. Compared with bulk CMOS, the superior electrostatic integrity and variability of FinFET enhance the feasibility of differential sensing in subthreshold SRAM applications.
Simulation of Grain-Boundary Induced V-th Variability in Stackable NAND Flash Using a Voronoi Approach
(2012)
Yang, Ching-Wei
;
Chao, Shao-Heng
;
Su, Pin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, we employ a novel Voronoi approach to simulate the impact of trap states in the poly-Si channel. Using this method, we investigate the grain boundary induced threshold voltage variability in stackable NAND flash memories. Our study indicates that considering the randomized shape and location of grain boundaries is crucial to the modeling and simulation of these devices.
A Novel Approach Using Discrete Grain-Boundary Traps to Study the Variability of 3-D Vertical-Gate NAND Flash Memory Cells
(2015-08-01)
Wang, Pei-Yu
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The 3-D NAND flash memory architectures will be a future trend, because they provide high memory capacity without aggressively scaling down. A vertical-gate (VG) structure composed of polysilicon (poly-Si) channels is a promising 3-D structure that could facilitate realizing an extremely tight-pitch NAND flash memory cell with high memory capacity. However, the variability of the VG memory cell induced by grain boundaries in the poly-Si channels is a major concern for aggressively scaled-down memory cells. In this paper, a discrete-trap approach is applied to emulate the real trap effects in a 3-D memory cell, and the 3-D structure geometry effects and the variation in the threshold voltage (V-T) induced by the discrete grain-boundary traps are studied. Various Delta V-T behaviors related to the structure geometry and trap position are examined. The effect of varying the body thickness on the Delta V-T is stronger than that of varying the channel width. This paper presents various cases for using the discrete-trap approach to study the variability of V-T in 3-D VG memory cells.
Design Optimization of 16-nm Bulk FinFET Technology via Geometric Programming
(2014-01-01)
Su, Ping-Hsun
;
Li, Yiming
;
傳播研究所
;
Institute of Communication Studies
Design rule is an important interface between design and manufacturing. It becomes more complex as the process advances to 16-nm and beyond. Current approaches to generate design rules are empirical shrink and lithographic simulation. However, it is time-consuming and costly to revise design rules for performance boost and yield improvement after design rules are frozen. Early performance gains in early design rule development without cost increase and yield loss will benefit semiconductor industry. In this work, we for the first time consider 16-nm bulk FinFET standard cell performance, yield, area, and layout style simultaneously to optimize design rules to meet ITRS by using geometric programming. Optical proximity correction, and electromagnetic field and circuit simulations are performed for objective function evaluation. The result achieves more than 100%-delay and 50%-yield improvement without area change by this systematic and statistical approach.
次32奈米多重閘極元件的特性分析與模式建立---變異性與微縮性，高頻類比特性，以及介觀現象的探討
(2008)
蘇彬
;
Su Pin
;
國立交通大學電子工程學系及電子研究所
在這個計畫中我們對次32 奈米多重閘極SOI CMOS 的元件特性作深入探討及模型建立。在工作項目一中，我們將建立一個適用於不同buried oxide 厚度的多重閘極SOI 元件的理論架構，我們的理論計算將涵蓋量子力學及原子等級的效應。我們的模型可用來預測次32 奈米多重閘極SOI 元件的電性變異及其可微縮性，將有助於多重閘極元件的設計。在工作項目二中，我們將綜合探討採用不同製程模組的多重閘極SOI 元件的高頻及類比特性。本研究可用來初步評估多重閘極SOI CMOS 技術在高頻及類比應用的發展潛力。在工作項目三中，我們將探討極小尺寸多重閘極元件的介觀現象。本研究對於瞭解次32 奈米多重閘極 SOI 電晶體的載子傳輸特性十分重要。
前瞻矽奈米元件變異性及傳輸特性綜合研究(I)
(2009)
蘇彬
;
Su Pin
;
國立交通大學電子工程學系及電子研究所
在此研究計畫中，我們將對以矽為基底的前瞻奈米元件，針對其變異性及載子傳輸特性，進行綜合研究。在工作項目一中，我們將分別對超薄基體(UTB)，多閘極(multi-gate)以及gate-all-around 奈米線金氧半場效電晶體，建立一套包含Poisson 及Schrodinger 方程式之解的理論架構。利用這一套可考慮量子效應的解析解模型，我們將研究這三種元件結構並搭配不同的通道材料，其對製程變異的敏感度。我們的元件模型也將有助於未來奈米級元件的設計。在工作項目二中，我們將廣泛地研究先進CMOS 場效電晶體的隨機不匹配特性(random mismatch)。這項研究不僅對使用先進CMOS 元件的電路設計很重要，也有助於對奈米元件的本質參數變異(intrinsic parameter fluctuation)的根本了解。在工作項目三中，我們將對奈米級應變矽元件的戴子傳輸特性進行研究。這項研究將有助於了解極微縮應變矽元件的戴子傳輸機制，也對未來提昇戴子遷移率的元件設計有所幫助。

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