ㄧ個全新的晶片-封裝-印刷電路板共同設計與共同最佳化方法

Abstract

因為現今的產品中SoC 與SiP 的設計需求有遽增的趨勢，因而快速的提高了晶片、封裝 與印刷電路板(PCB)的設計困難度。為了應付更多數量的輸出入接腳(I/O pin)、更高速的訊號 以及更密集的晶片密度等問題，IC 設計工程師常使用覆晶封裝(flip-chip package)的方式來取 代一般打線封裝(wire-bond package)設計。然而，傳統的覆晶封裝—印刷電路板共同設計 (package-board codesign)以手動方式安排接腳位置，不但耗時、效率低而且必須完全仰賴工 程師的經驗。本計劃即提出一個可以自動安排封裝接腳位置與最佳化封裝尺寸的設計流程。 此計劃共分成三個部份﹕首先，我們將建立一組可以同時考慮訊號完整性(Signal integrity)、電源供應(Power delivery)與可繞線率(Routability)的訊號—接腳樣板(Signal-pin pattern)，利用這些樣板建構訊號—接腳區塊(Signal-pin block)，最後再以一區塊擺置演算法 (Block floorplanning algorithm)完成最後的接腳位置圖並且達到最小的封裝尺寸。第二部份， 我們將試著應用IC 內部區塊擺置(Floorplanning)的方法來安排訊號—接腳區塊已達到晶片效 能與成本的最佳化，例如使用『範圍限制(Range constraint)』與『模擬退火技術(Simulated annealing technique)』。最後，我們會建立一組IC、封裝與印刷電路板模型(Model)，並且提 出一個完整的晶片—封裝—印刷電路板共同設計流程(Chip-package-board codesign flow)，在 此設計流程中得以共同模擬(Co-simulation)與共同最佳化(Co-optimization)。

Due to the trend of more and more SoC and SiP projects, the complication in package designs and signal interaction between package and board is increasing very rapidly. Since the typical peripheral wire-bond design may not be appropriate for some particular designs, flip-chip package becomes a better choice. In conventional flip-chip package-board codesign, engineers designate the pin-out manually, which is very time-consuming and always postpones the time-to-market (TTM) of products. This project will propose a method of automatically generating the BGA pin-out by pin-block design and floorplanning, thus speed up the developing time dramatically. The project contains three parts (for three years): first, we propose the signal-pin patterns for pin-block construction in package design. Signal integrity, power delivery, and routability will be accounted for in those patterns. This helps to speed up the process of pin-out designation. And then we propose a near optimal approach to minimizing package size by mathematical programming formulation. Second, we will try to develop a novel planning algorithm by using a new representation for pin-block placement and defining range constraints in simulated annealing technique to optimize the location of pin-blocks. Finally, we will establish the chip-package-board codesign flow and create package-interconnection models. Then chip and package are co-simulated and co-optimized.