微瓦級動態電壓與頻率調整之晶片匯流排設計

Full metadata record

DC Field	Value	Language
dc.contributor.author	蘇朝琴	en_US
dc.contributor.author	SU CHAU-CHIN	en_US
dc.date.accessioned	2014-12-13T10:45:16Z	-
dc.date.available	2014-12-13T10:45:16Z	-
dc.date.issued	2010	en_US
dc.identifier.govdoc	NSC98-2221-E009-137-MY2	zh_TW
dc.identifier.uri	http://hdl.handle.net/11536/100321	-
dc.identifier.uri	https://www.grb.gov.tw/search/planDetail?id=2012195&docId=329353	en_US
dc.description.sponsorship	行政院國家科學委員會	zh_TW
dc.language.iso	zh_TW	en_US
dc.title	微瓦級動態電壓與頻率調整之晶片匯流排設計	zh_TW
dc.title	The Design of UW DVFS On-Chip Bus	en_US
dc.type	Plan	en_US
dc.contributor.department	國立交通大學電機與控制工程學系（所）	zh_TW
Appears in Collections:	Research Plans