標題: A platform-based SoC design and implementation of scalable automaton matching for deep packet inspection
作者: Lin, Ying-Dar
Tseng, Kuo-Kun
Lee, Tsern-Huei
Lin, Yi-Neng
Hung, Chen-Chou
Lai, Yuan-Cheng
資訊工程學系
電信工程研究所
Department of Computer Science
Institute of Communications Engineering
關鍵字: deep packet inspection;automaton;string matching;content filtering
公開日期: 1-十二月-2007
摘要: String matching plays a central role in packet inspection applications such as intrusion detection, anti-virus, anti-sparn and Web filtering. Since they are computation and memory intensive, software matching algorithms are insufficient to meet the high-speed performance. Thus, offloading packet inspection to a dedicated hardware seems inevitable. This paper presents a scalable automaton matching (SAM) coprocessor that uses Aho-Corasick (AC) algorithm with two parallel acceleration techniques, root-indexing and pre-hashing. The root-indexing can match multiple bytes in one single matching, and the pre-hashing can be used to avoid bitmap, AC matching which is a cycle-consuming operation. In the platform-based SoC implementation of the Xilinx ML310 FPGA, the proposed hardware architecture can achieve almost 10.7 Gbps and support over 10,000 patterns for virus, which is the largest pattern set from among the existing works. On the average, the performance of SAM is 7.65 times faster than the original bitmap AC. Furthermore, SAM is feasible for either internal or external memory architecture. The internal memory architecture provides high performance, while the external memory architecture provides high scalability in term of the number of patterns. (C) 2007 Elsevier B.V. All rights reserved.
URI: http://dx.doi.org/10.1016/j.sysarc.2007.03.005
http://hdl.handle.net/11536/10041
ISSN: 1383-7621
DOI: 10.1016/j.sysarc.2007.03.005
期刊: JOURNAL OF SYSTEMS ARCHITECTURE
Volume: 53
Issue: 12
起始頁: 937
結束頁: 950
顯示於類別:期刊論文


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