次32奈米CMOS元件可靠性分析、量子結構效應、與蒙地卡羅電荷傳輸模擬

Abstract

當CMOS 元件微縮至32 奈米以下，無論在元件結構,材料與載子傳輸理論方面，均將發生重 大變化與挑戰。在本計劃內，吾人將針對先進CMOS 元件，例如,含形變之矽/鍺通道，高介電係 數/金屬閘極及具量子結構之元件，進行理論與實驗研究。在可靠度方面，吾人將延續在前期計畫 中所發展之單電子量測技術，研究新式閘極介電層材料之缺陷及其對載子移動率(carrier mobility) 之影響，並探討限制元件微縮之可靠性議題，如電流雜訊等。 在理論計算方面，吾人將以先前所發展之蒙地卡羅模擬為基礎，並配合載子能帶結構之計 算，研究各種增進載子移動率之技術，內容涵蓋具形變之元件通道，極短通道內載子之特殊傳輸 效應(velocity overshoot and ballistic motion)，及具量子結構之元件特性(例如FinFET, quantum well channel)，上述研究將著重於含量子結構與形變能帶結構之計算，綜合本計劃之研究目標，一為 利用吾人在元件可靠性量測方法之突破(單電子效應量測)，探討元件在微縮過程中新的材料與新 的元件結構所產生可靠性議題及相關物理機制，另一方面，針對目前各種新式元件提供一具量子 效應之蒙地卡羅模擬，以探討各種增進載子速度方法之理論基礎與極限。

As CMOS devices are scaled beyond 32nm technology node, drastic changes and many new challenges are expected no matter in device structures, channel and gate materials and charge transport theory. In this project, we will launch a multi-year effort to explore charge transport and mobility degradation/enhancement mechanisms in various newly evolved CMOS devices, such as strained Si/Ge channel, high-k/metal gate and quantum CMOS structures. With respect to device reliability, we will focus on single charge phenomena and current fluctuations in scaled CMOS. We have demonstrated that single charge effects are more prominent as CMOS is scaled. By analyzing data from single charge phenomena, we can obtain more information about trap properties and open a new research direction in device reliability. In the theoretical part, we will use our previously developed Monte Carlo simulation to study various mobility degradation/enhancement mechanisms, including strain and channel orientation effects, quantum confinement and sub-band structures, velocity overshoot and ultimately ballistic motion in ultra-short channel CMOS. A bond orbital model for heavy-hole, light-hole and split-off bands including confinement potential and strain Hamiltonian will be employed in our Monte Carlo for hole transport. Newly invented CMOS structures such as DG FET/FinFET, quantum well Ge channel can be also evaluated. The objectives of this project are two-fold; First, we will use our single charge characterization technique, combined with other methods, to identify new reliability issues and constraints in device scaling. Second, we will use Monte Carlo to provide theoretical basis for various mobility enhancement techniques.