嵌入式DRAM測試方法

Abstract

在系統晶片的時代，我們須要有效率且經濟的嵌入式記憶體，研究人員嘗試著將獨立DRAM的優點，帶進系統晶片中。於是，過去的十年當中，許多研究資源已經投入到嵌入式DRAM（eDRAM）的領域，嘗試著將eDRAM對於邏輯製程來說的額外製程負擔降低。然而，現有的文獻裡面，幾乎沒有研究在討論eDRAM的測試，然而傳統獨立式DRAM的測試，是沒有辦法直接用在eDRAM測試上的。 既然eDRAM使用了DRAM的記憶體單元以及SRAM的介面，在本計畫當中，我們首先比較eDRAM測試，與獨立式DRAM測試以及SRAM測試的不同。接著我們整理出在eDRAM測試中所需要特別注意的錯誤模型，以及可以測到這些錯誤模型所需的測試圖案。本計畫的主要目標有三：（一） 研發出一最短的eDRAM測試演算法；（二）研發出如何有效利用提升溫度，達到降低資料延遲測試在eSRAM測試中的時間；（三）研發出一數學模型，用以估計在使用ECC(錯誤修正碼)的情況下，eDRAM受到磨損瑕疵所產生的瑕疵程度。其中ECC是eDRAM特有，而獨立式DRAM中沒有的功能。

With the strong need to an effective and economic embedded-memory core in the SoC era, researchers attempt to carry commodity DRAM's advantages from a commodity memory into a SoC. In the past decade, a lot research effort has been put into the area of the embedded-DRAM (eDRAM) technologies to reduce eDRAM's process adders to the CMOS process. However, few previous research works have discussed the testing strategies used for eDRAMs, which cannot be directly carried from the testing of commodity DRAMs. In this project, we first compare the eDRAM testing to the commodity-DRAM testing and SRAM testing since an eDRAM core utilizes the DRAM cells with the SRAM interface. Then, we list the fault models which should be specially considered in the eDRAM testing and find out the corresponding test sequence for each fault model. The main objectives of this project include (1) develop a minimal test algorithm for eDRAM testing, (2) develop an effective scheme to shorten the retention-test time in eDRAM testing based on increasing the temperature, and (3) develop a mathematical model to estimate the defect level caused by wear-out defects under the use of ECC circuitry, which is a special function used in eDRAMs compared to commodity DRAMs.