在矽基板整合40奈米三五族與鍺量子井場效電晶體作為低功率與高速無線之應用(I)

Abstract

矽半導體技術，發展至30 奈米已面臨瓶頸，需有高載子遷移率材料加入，以使技 術得以持續發展，三五量子井場效電晶體或稱調變摻雜場效電晶體為現今所知速度最快 之場效電晶體，具有高速、低功率特性，但因為三五族材料之低電洞遷移率使其無法製 作互補的結構，本計畫即利用高電洞遷移率鍺通道與高電子遷移率的三五材料透過矽鍺 緩衝層成長在矽晶片來解決此問題。 在本計畫，三五n 型元件將利用矽鍺與砷化銦鋁假晶緩衝層成長在矽基板，通道 將採用砷化銦鎵，n 型施體層將使用砷化銦鋁。P 型元件將會製作在釋放應力矽鍺緩衝 層，電洞提供層將使用矽、矽鍺或砷化鎵。 本研究將整合材料成長、新穎元件結構、元件製造技術、發展三五族鍺通道量子 井電晶體，作為發展新世代半導體技術，作為高速數位與超高頻寬微波連線應用。此 一元件將可應用在220 GHz 無線的通訊與光纎通信系統。此外本計畫發展之量子井元 件更可整合在22 奈米以下CMOS 技術作為低功率晶片無線互連之應用，將為下世代 晶片信號連結展開新的一頁。 施敏教授，張俊彥教授，美國英代爾半導體Dr. Robert Chau，日本工學大學Prof. Hiroshi Iwai 與瑞典查默爾大學Prof. Herbert Zirath 等世界知名專家將參與本學術卓越 計畫之執行及技術顧問。

The III-V modulation doped FET (MODFET) offers the highest device speed as well as low power capability and low noise performance. However, the low hole mobility of III-V material makes the complementary structures not possible using the III-V channel. There is a need for p-channel FETs with very high hole mobility for future advanced nano electronic applications. These problems can be solved by growing the SiGe buffer layer on Si as the templates for high-hole-mobility Ge channel and high-electron-mobility III-V materials, such as, InxGa1-xAs or InAs with the complementary circuitry architecture. Current MODFET structure using the quantum well channel for carrier transport has higher carrier mobility compared to the MOSFET structures. Moreover, the gate leakage current and the dynamic power dissipation of the Quantum-Well-based MODFETs can be further improved by a metal-oxide-semiconductor gate stack on modulation-doped III-V and Ge channel to replace the conventional Schottky gate. Different device architectures will be investigated on the QWFETs (Quantum Well FET) for performance improvement. Furthermore, effect of the gate length reduction down to 40 nm with T-shaped gate will be studied. To provide better integration among various device technologies, III-V and Ge QWFETs will be integrated on a Si Substrate. The III-V QWFETs will be grown on Si substrate using SiGe buffer combined with InAlAs metamorphic buffer and Selective Epitaxial Growth. The channel will be InAs layer and InAlAs with delta doped Si as the n-type donating layer. Meanwhile, the Ge channel will be grown on relaxed SiGe buffer with p-type doped Si or SiGe or GaAs layer as hole supply layers. Si can be either on the top of Ge channel or on the bottom of Ge channel depending on the device architecture. The high carrier mobility can be even enhanced through the strain engineering, substrate orientation selection, channel direction selection, and combination of previous mentioned technologies. This project proposes a complete research roadmap from basic study of material growth; innovative device structures, fabrication technology, and device characterization all the way to system level integration for high speed digital and ultra high bandwidth RF interconnect applications. Such high frequency and low power features of III-V and Ge QWFETs make the integrated architecture particularly useful in next generation wireless applications with frequency beyond 60 GHz and up to several hundred GHz for sub-millimeter wave tele-comunications or photonic network systems. The developed QWFETs can further be integrated with 22nm and beyond CMOS technology for low power chip link for energy saving interconnects between chips which have been identified as an imminent application of the next century. The research team has developed several key technologies and collaborated with Intel Corporation for joint development on the III-V InAs based QWFETs for low power and high speed digital applications. Besides, Dr. Simon Sze will be the international advisory for the project. World-class partners on high speed devices (C.Y.Chang, NCTU) will join this project for complementary technology development with endorsement from Robert Chau (Research Director of Intel Headquarter) for long-term relationship and technology advisory.